diff mbox series

[v3,22/40] target/mips: Add handling of branch delay slots for nanoMIPS

Message ID 1532004912-13899-23-git-send-email-stefan.markovic@rt-rk.com
State New
Headers show
Series Add nanoMIPS support to QEMU | expand

Commit Message

Stefan Markovic July 19, 2018, 12:54 p.m. UTC 
From: Matthew Fortune <matthew.fortune@mips.com>

ISA mode bit (LSB of address) is no longer required but is also
masked to allow for tools transition. The flag has_isa_mode has the
key role in the implementation.

Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
 target/mips/translate.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

Comments

Richard Henderson July 21, 2018, 6:03 p.m. UTC | #1 
On 07/19/2018 05:54 AM, Stefan Markovic wrote:
> @@ -10991,7 +10992,8 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
>              break;
>          case MIPS_HFLAG_BR:
>              /* unconditional branch to register */
> -            if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) {
> +            if (ctx->has_isa_mode &&
> +                    (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS))) {

Is this second condition really ever true for ISA_NANOMIPS?

> @@ -24747,6 +24749,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>      ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
>      ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
>      ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
> +    ctx->has_isa_mode = ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) != 3;

< 3?

Or perhaps merge the combined test here,

  ctx->has_isa_mode = (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS))
                   && ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) < 3);

and only use ctx->has_isa_mode in the other locations.



r~
diff mbox series

Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index d7454a6..7fb2ff9 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1458,6 +1458,7 @@  typedef struct DisasContext {
     bool mrp;
     bool nan2008;
     bool abs2008;
+    bool has_isa_mode;
 } DisasContext;
 
 #define DISAS_STOP       DISAS_TARGET_0
@@ -4538,7 +4539,7 @@  static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
 
     if (blink > 0) {
         int post_delay = insn_bytes + delayslot_size;
-        int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
+        int lowbit = ctx->has_isa_mode && !!(ctx->hflags & MIPS_HFLAG_M16);
 
         tcg_gen_movi_tl(cpu_gpr[blink],
                         ctx->base.pc_next + post_delay + lowbit);
@@ -10991,7 +10992,8 @@  static void gen_branch(DisasContext *ctx, int insn_bytes)
             break;
         case MIPS_HFLAG_BR:
             /* unconditional branch to register */
-            if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) {
+            if (ctx->has_isa_mode &&
+                    (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS))) {
                 TCGv t0 = tcg_temp_new();
                 TCGv_i32 t1 = tcg_temp_new_i32();
 
@@ -11027,7 +11029,7 @@  static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
     int bcond_compute = 0;
     TCGv t0 = tcg_temp_new();
     TCGv t1 = tcg_temp_new();
-    int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0;
+    int m16_lowbit = ctx->has_isa_mode && ((ctx->hflags & MIPS_HFLAG_M16) != 0);
 
     if (ctx->hflags & MIPS_HFLAG_BMASK) {
 #ifdef MIPS_DEBUG_DISAS
@@ -24747,6 +24749,7 @@  static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
     ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
     ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
+    ctx->has_isa_mode = ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) != 3;
     restore_cpu_state(env, ctx);
 #ifdef CONFIG_USER_ONLY
         ctx->mem_idx = MIPS_HFLAG_UM;