From patchwork Thu Jul 19 12:54:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946379 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbPM0Bv1z9s7c for ; Fri, 20 Jul 2018 00:04:53 +1000 (AEST) Received: from localhost ([::1]:43215 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9Y2-0007jR-8V for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:04:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53673) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Xm-0003nZ-D8 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:03:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Ua-0005jb-DV for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:00:30 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57050 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8UZ-0005iQ-OJ for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:57:12 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 504EB1A4574; Thu, 19 Jul 2018 14:57:10 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 328391A4570; Thu, 19 Jul 2018 14:57:10 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:46 +0200 Message-Id: <1532004912-13899-15-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 14/40] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Add emulation of misc nanoMIPS instructions situated in pool32axf. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic Reviewed-by: Richard Henderson --- target/mips/translate.c | 94 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 81c2950..af7825a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16768,6 +16768,93 @@ static void gen_pool32a0_nanomips_insn(DisasContext *ctx) } } +static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) +{ + int rt = (ctx->opcode >> 21) & 0x1f; + int rs = (ctx->opcode >> 16) & 0x1f; + + switch ((ctx->opcode >> 6) & 0x07) { + case NM_POOL32AXF_4: + case NM_POOL32AXF_5: + switch ((ctx->opcode >> 9) & 0x7f) { + case NM_CLO: + gen_cl(ctx, OPC_CLO, rt, rs); + break; + case NM_CLZ: + gen_cl(ctx, OPC_CLZ, rt, rs); + break; +#ifndef CONFIG_USER_ONLY + case NM_TLBP: + gen_cp0(env, ctx, OPC_TLBP, 0, 0); + break; + case NM_TLBR: + gen_cp0(env, ctx, OPC_TLBR, 0, 0); + break; + case NM_TLBWI: + gen_cp0(env, ctx, OPC_TLBWI, 0, 0); + break; + case NM_TLBWR: + gen_cp0(env, ctx, OPC_TLBWR, 0, 0); + break; + case NM_TLBINV: + gen_cp0(env, ctx, OPC_TLBINV, 0, 0); + break; + case NM_TLBINVF: + gen_cp0(env, ctx, OPC_TLBINVF, 0, 0); + break; + case NM_DI: + check_cp0_enabled(ctx); + { + TCGv t0 = tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_helper_di(t0, cpu_env); + gen_store_gpr(t0, rt); + /* Stop translation as we may have switched the execution mode */ + ctx->base.is_jmp = DISAS_STOP; + tcg_temp_free(t0); + } + break; + case NM_EI: + check_cp0_enabled(ctx); + { + TCGv t0 = tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_helper_ei(t0, cpu_env); + gen_store_gpr(t0, rt); + /* Stop translation as we may have switched the execution mode */ + ctx->base.is_jmp = DISAS_STOP; + tcg_temp_free(t0); + } + break; + case NM_RDPGPR: + gen_load_srsgpr(rs, rt); + break; + case NM_WRPGPR: + gen_store_srsgpr(rs, rt); + break; + case NM_WAIT: + gen_cp0(env, ctx, OPC_WAIT, 0, 0); + break; + case NM_DERET: + gen_cp0(env, ctx, OPC_DERET, 0, 0); + break; + case NM_ERETX: + gen_cp0(env, ctx, OPC_ERET, 0, 0); + break; +#endif + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } +} + static void gen_pool32f_nanomips_insn(DisasContext *ctx) { int rt, rs, rd; @@ -17137,6 +17224,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_pool32a0_nanomips_insn(ctx); break; case NM_POOL32A7: + { + switch ((ctx->opcode >> 3) & 0x07) { + case NM_POOL32AXF: + gen_pool32axf_nanomips_insn(env, ctx); + break; + } + } break; default: generate_exception_end(ctx, EXCP_RI);