From patchwork Thu Jul 19 12:54:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946314 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WZm25FCSz9s55 for ; Thu, 19 Jul 2018 23:36:01 +1000 (AEST) Received: from localhost ([::1]:43002 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg964-0007pR-ST for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:35:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49211) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Vd-0003Br-Ox for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Sv-00042r-Pd for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:58:17 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:55215 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8Sv-00041p-D6 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:55:29 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id DC19D1A4156; Thu, 19 Jul 2018 14:55:27 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id BF9B91A1D42; Thu, 19 Jul 2018 14:55:27 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:33 +0200 Message-Id: <1532004912-13899-2-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 01/40] target/mips: Add preprocessor constants for nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Add ISA_NANOMIPS32 and CPU_NANOMIPS32 preprocessor constants. Reviewed-by: Richard Henderson Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/mips-defs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index d239069..c8e9979 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -39,6 +39,7 @@ #define ISA_MIPS64R5 0x00001000 #define ISA_MIPS32R6 0x00002000 #define ISA_MIPS64R6 0x00004000 +#define ISA_NANOMIPS32 0x00008000 /* MIPS ASEs. */ #define ASE_MIPS16 0x00010000 @@ -87,6 +88,9 @@ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) +/* Wave Computing: "nanoMIPS" */ +#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) + /* Strictly follow the architecture standard: - Disallow "special" instruction handling for PMON/SPIM. Note that we still maintain Count/Compare to match the host clock. */ From patchwork Thu Jul 19 12:54:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946385 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbVV4Tycz9s4r for ; Fri, 20 Jul 2018 00:09:22 +1000 (AEST) Received: from localhost ([::1]:43247 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9cO-0003Pr-9T for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:09:20 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48016) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Yw-0004M4-IL for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:05:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8T2-00048q-Gx for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:56:42 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:55256 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8T1-00047e-BD for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:55:36 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id F046A1A4542; Thu, 19 Jul 2018 14:55:33 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id CF4AA1A44FF; Thu, 19 Jul 2018 14:55:33 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:34 +0200 Message-Id: <1532004912-13899-3-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 02/40] target/mips: Add nanoMIPS base instruction set opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Add nanoMIPS opcodes. nanoMIPS instruction are organized by so-called instruction pools. Each pool contains a set of opcodes, that in turn can be instruction opcodes or instruction pool opcodes. Reviewed-by: Richard Henderson Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 670 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 670 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index de0d55b..6a99a61 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -15644,6 +15644,676 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx) return 2; } +/* + * + * nanoMIPS opcodes + * + */ + +/* MAJOR, P16, and P32 pools opcodes */ +enum { + NM_P_ADDIU = 0x00, + NM_ADDIUPC = 0x01, + NM_MOVE_BALC = 0x02, + NM_P16_MV = 0x04, + NM_LW16 = 0x05, + NM_BC16 = 0x06, + NM_P16_SR = 0x07, + + NM_POOL32A = 0x08, + NM_P_BAL = 0x0a, + NM_P16_SHIFT = 0x0c, + NM_LWSP16 = 0x0d, + NM_BALC16 = 0x0e, + NM_P16_4X4 = 0x0f, + + NM_P_GP_W = 0x10, + NM_P_GP_BH = 0x11, + NM_P_J = 0x12, + NM_P16C = 0x14, + NM_LWGP16 = 0x15, + NM_P16_LB = 0x17, + + NM_P48I = 0x18, + NM_P16_A1 = 0x1c, + NM_LW4X4 = 0x1d, + NM_P16_LH = 0x1f, + + NM_P_U12 = 0x20, + NM_P_LS_U12 = 0x21, + NM_P_BR1 = 0x22, + NM_P16_A2 = 0x24, + NM_SW16 = 0x25, + NM_BEQZC16 = 0x26, + + NM_POOL32F = 0x28, + NM_P_LS_S9 = 0x29, + NM_P_BR2 = 0x2a, + + NM_P16_ADDU = 0x2c, + NM_SWSP16 = 0x2d, + NM_BNEZC16 = 0x2e, + NM_MOVEP = 0x2f, + + NM_POOL32S = 0x30, + NM_P_BRI = 0x32, + NM_LI16 = 0x34, + NM_SWGP16 = 0x35, + NM_P16_BR = 0x36, + + NM_P_LUI = 0x38, + NM_ANDI16 = 0x3c, + NM_SW4X4 = 0x3d, + NM_MOVEPREV = 0x3f, +}; + +/* POOL32A instruction pool */ +enum { + NM_POOL32A0 = 0x00, + NM_SPECIAL2 = 0x01, + NM_COP2_1 = 0x02, + NM_UDI = 0x03, + NM_POOL32A5 = 0x05, + NM_POOL32A7 = 0x07, +}; + +/* P.GP.W instruction pool */ +enum { + NM_ADDIUGP_W = 0x00, + NM_LWGP = 0x02, + NM_SWGP = 0x03, +}; + +/* P48I instruction pool */ +enum { + NM_LI48 = 0x00, + NM_ADDIU48 = 0x01, + NM_ADDIUGP48 = 0x02, + NM_ADDIUPC48 = 0x03, + NM_LWPC48 = 0x0b, + NM_SWPC48 = 0x0f, +}; + +/* P.U12 instruction pool */ +enum { + NM_ORI = 0x00, + NM_XORI = 0x01, + NM_ANDI = 0x02, + NM_P_SR = 0x03, + NM_SLTI = 0x04, + NM_SLTIU = 0x05, + NM_SEQI = 0x06, + NM_ADDIUNEG = 0x08, + NM_P_SHIFT = 0x0c, + NM_P_ROTX = 0x0d, + NM_P_INS = 0x0e, + NM_P_EXT = 0x0f, +}; + +/* POOL32F instruction pool */ +enum { + NM_POOL32F_0 = 0x00, + NM_POOL32F_3 = 0x03, + NM_POOL32F_5 = 0x05, +}; + +/* POOL32S instruction pool */ +enum { + NM_POOL32S_0 = 0x00, + NM_POOL32S_4 = 0x04, +}; + +/* P.LUI instruction pool */ +enum { + NM_LUI = 0x00, + NM_ALUIPC = 0x01, +}; + +/* P.GP.BH instruction pool */ +enum { + NM_LBGP = 0x00, + NM_SBGP = 0x01, + NM_LBUGP = 0x02, + NM_ADDIUGP_B = 0x03, + NM_P_GP_LH = 0x04, + NM_P_GP_SH = 0x05, + NM_P_GP_CP1 = 0x06, +}; + +/* P.LS.U12 instruction pool */ +enum { + NM_LB = 0x00, + NM_SB = 0x01, + NM_LBU = 0x02, + NM_P_PREFU12 = 0x03, + NM_LH = 0x04, + NM_SH = 0x05, + NM_LHU = 0x06, + NM_LWU = 0x07, + NM_LW = 0x08, + NM_SW = 0x09, + NM_LWC1 = 0x0a, + NM_SWC1 = 0x0b, + NM_LDC1 = 0x0e, + NM_SDC1 = 0x0f, +}; + +/* P.LS.S9 instruction pool */ +enum { + NM_P_LS_S0 = 0x00, + NM_P_LS_S1 = 0x01, + NM_P_LS_E0 = 0x02, + NM_P_LS_WM = 0x04, + NM_P_LS_UAWM = 0x05, +}; + +/* P.BAL instruction pool */ +enum { + NM_BC = 0x00, + NM_BALC = 0x01, +}; + +/* P.J instruction pool */ +enum { + NM_JALRC = 0x00, + NM_JALRC_HB = 0x01, + NM_P_BALRSC = 0x08, +}; + +/* P.BR1 instruction pool */ +enum { + NM_BEQC = 0x00, + NM_P_BR3A = 0x01, + NM_BGEC = 0x02, + NM_BGEUC = 0x03, +}; + +/* P.BR2 instruction pool */ +enum { + NM_BNEC = 0x00, + NM_BLTC = 0x02, + NM_BLTUC = 0x03, +}; + +/* P.BRI instruction pool */ +enum { + NM_BEQIC = 0x00, + NM_BBEQZC = 0x01, + NM_BGEIC = 0x02, + NM_BGEIUC = 0x03, + NM_BNEIC = 0x04, + NM_BBNEZC = 0x05, + NM_BLTIC = 0x06, + NM_BLTIUC = 0x07, +}; + +/* P16.SHIFT instruction pool */ +enum { + NM_SLL16 = 0x00, + NM_SRL16 = 0x01, +}; + +/* POOL16C instruction pool */ +enum { + NM_POOL16C_0 = 0x00, + NM_LWXS16 = 0x01, +}; + +/* P16.A1 instruction pool */ +enum { + NM_ADDIUR1SP = 0x01, +}; + +/* P16.A2 instruction pool */ +enum { + NM_ADDIUR2 = 0x00, + NM_P_ADDIURS5 = 0x01, +}; + +/* P16.ADDU instruction pool */ +enum { + NM_ADDU16 = 0x00, + NM_SUBU16 = 0x01, +}; + +/* P16.SR instruction pool */ +enum { + NM_SAVE16 = 0x00, + NM_RESTORE_JRC16 = 0x01, +}; + +/* P16.4X4 instruction pool */ +enum { + NM_ADDU4X4 = 0x00, + NM_MUL4X4 = 0x01, +}; + +/* P16.LB instruction pool */ +enum { + NM_LB16 = 0x00, + NM_SB16 = 0x01, + NM_LBU16 = 0x02, +}; + +/* P16.LH instruction pool */ +enum { + NM_LH16 = 0x00, + NM_SH16 = 0x01, + NM_LHU16 = 0x02, +}; + +/* P.RI instruction pool */ +enum { + NM_SIGRIE = 0x00, + NM_P_SYSCALL = 0x01, + NM_BREAK = 0x02, + NM_SDBBP = 0x03, +}; + +/* POOL32A0 instruction pool */ +enum { + NM_P_TRAP = 0x00, + NM_SEB = 0x01, + NM_SLLV = 0x02, + NM_MUL = 0x03, + NM_MFC0 = 0x06, + NM_MFHC0 = 0x07, + NM_SEH = 0x09, + NM_SRLV = 0x0a, + NM_MUH = 0x0b, + NM_MTC0 = 0x0e, + NM_MTHC0 = 0x0f, + NM_SRAV = 0x12, + NM_MULU = 0x13, + NM_ROTRV = 0x1a, + NM_MUHU = 0x1b, + NM_ADD = 0x22, + NM_DIV = 0x23, + NM_ADDU = 0x2a, + NM_MOD = 0x2b, + NM_SUB = 0x32, + NM_DIVU = 0x33, + NM_RDHWR = 0x38, + NM_SUBU = 0x3a, + NM_MODU = 0x3b, + NM_P_CMOVE = 0x42, + NM_FORK = 0x45, + NM_MFTR = 0x46, + NM_MFHTR = 0x47, + NM_AND = 0x4a, + NM_YIELD = 0x4d, + NM_MTTR = 0x4e, + NM_MTHTR = 0x4f, + NM_OR = 0x52, + NM_D_E_MT_VPE = 0x56, + NM_NOR = 0x5a, + NM_XOR = 0x62, + NM_SLT = 0x6a, + NM_P_SLTU = 0x72, + NM_SOV = 0x7a, +}; + +/* POOL32A7 instruction pool */ +enum { + NM_P_LSX = 0x00, + NM_LSA = 0x01, + NM_EXTW = 0x03, + NM_POOL32AXF = 0x07, +}; + +/* P.SR instruction pool */ +enum { + NM_PP_SR = 0x00, + NM_P_SR_F = 0x01, +}; + +/* P.SHIFT instruction pool */ +enum { + NM_P_SLL = 0x00, + NM_SRL = 0x02, + NM_SRA = 0x04, + NM_ROTR = 0x06, +}; + +/* P.ROTX instruction pool */ +enum { + NM_ROTX = 0x00, +}; + +/* P.INS instruction pool */ +enum { + NM_INS = 0x00, +}; + +/* P.EXT instruction pool */ +enum { + NM_EXT = 0x00, +}; + +/* POOL32F_0 (fmt) instruction pool */ +enum { + NM_RINT_S = 0x04, + NM_RINT_D = 0x44, + NM_ADD_S = 0x06, + NM_SELEQZ_S = 0x07, + NM_SELEQZ_D = 0x47, + NM_CLASS_S = 0x0c, + NM_CLASS_D = 0x4c, + NM_SUB_S = 0x0e, + NM_SELNEZ_S = 0x0f, + NM_SELNEZ_D = 0x4f, + NM_MUL_S = 0x16, + NM_SEL_S = 0x17, + NM_SEL_D = 0x57, + NM_DIV_S = 0x1e, + NM_ADD_D = 0x26, + NM_SUB_D = 0x2e, + NM_MUL_D = 0x36, + NM_MADDF_S = 0x37, + NM_MADDF_D = 0x77, + NM_DIV_D = 0x3e, + NM_MSUBF_S = 0x3f, + NM_MSUBF_D = 0x7f, +}; + +/* POOL32F_3 instruction pool */ +enum { + NM_MIN_FMT = 0x00, + NM_MAX_FMT = 0x01, + NM_MINA_FMT = 0x04, + NM_MAXA_FMT = 0x05, + NM_POOL32FXF = 0x07, +}; + +/* POOL32F_5 instruction pool */ +enum { + NM_CMP_CONDN_S = 0x00, + NM_CMP_CONDN_D = 0x02, +}; + +/* P.GP.LH instruction pool */ +enum { + NM_LHGP = 0x00, + NM_LHUGP = 0x01, +}; + +/* P.GP.SH instruction pool */ +enum { + NM_SHGP = 0x00, +}; + +/* P.GP.CP1 instruction pool */ +enum { + NM_LWC1GP = 0x00, + NM_SWC1GP = 0x01, + NM_LDC1GP = 0x02, + NM_SDC1GP = 0x03, +}; + +/* P.LS.S0 instruction pool */ +enum { + NM_LBS9 = 0x00, + NM_LHS9 = 0x04, + NM_LWS9 = 0x08, + NM_LDS9 = 0x0c, + + NM_SBS9 = 0x01, + NM_SHS9 = 0x05, + NM_SWS9 = 0x09, + NM_SDS9 = 0x0d, + + NM_LBUS9 = 0x02, + NM_LHUS9 = 0x06, + NM_LWC1S9 = 0x0a, + NM_LDC1S9 = 0x0e, + + NM_P_PREFS9 = 0x03, + NM_LWUS9 = 0x07, + NM_SWC1S9 = 0x0b, + NM_SDC1S9 = 0x0f, +}; + +/* P.LS.S1 instruction pool */ +enum { + NM_ASET_ACLR = 0x02, + NM_UALH = 0x04, + NM_UASH = 0x05, + NM_CACHE = 0x07, + NM_P_LL = 0x0a, + NM_P_SC = 0x0b, +}; + +/* P.LS.WM instruction pool */ +enum { + NM_LWM = 0x00, + NM_SWM = 0x01, +}; + +/* P.LS.UAWM instruction pool */ +enum { + NM_UALWM = 0x00, + NM_UASWM = 0x01, +}; + +/* P.BR3A instruction pool */ +enum { + NM_BC1EQZC = 0x00, + NM_BC1NEZC = 0x01, + NM_BC2EQZC = 0x02, + NM_BC2NEZC = 0x03, + NM_BPOSGE32C = 0x04, +}; + +/* P16.RI instruction pool */ +enum { + NM_P16_SYSCALL = 0x01, + NM_BREAK16 = 0x02, + NM_SDBBP16 = 0x03, +}; + +/* POOL16C_0 instruction pool */ +enum { + NM_POOL16C_00 = 0x00, +}; + +/* P16.JRC instruction pool */ +enum { + NM_JRC = 0x00, + NM_JALRC16 = 0x01, +}; + +/* P.SYSCALL instruction pool */ +enum { + NM_SYSCALL = 0x00, + NM_HYPCALL = 0x01, +}; + +/* P.TRAP instruction pool */ +enum { + NM_TEQ = 0x00, + NM_TNE = 0x01, +}; + +/* P.CMOVE instruction pool */ +enum { + NM_MOVZ = 0x00, + NM_MOVN = 0x01, +}; + +/* POOL32Axf instruction pool */ +enum { + NM_POOL32AXF_4 = 0x04, + NM_POOL32AXF_5 = 0x05, +}; + +/* POOL32Axf_{4, 5} instruction pool */ +enum { + NM_CLO = 0x25, + NM_CLZ = 0x2d, + + NM_TLBP = 0x01, + NM_TLBR = 0x09, + NM_TLBWI = 0x11, + NM_TLBWR = 0x19, + NM_TLBINV = 0x03, + NM_TLBINVF = 0x0b, + NM_DI = 0x23, + NM_EI = 0x2b, + NM_RDPGPR = 0x70, + NM_WRPGPR = 0x78, + NM_WAIT = 0x61, + NM_DERET = 0x71, + NM_ERETX = 0x79, +}; + +/* PP.SR instruction pool */ +enum { + NM_SAVE = 0x00, + NM_RESTORE = 0x02, + NM_RESTORE_JRC = 0x03, +}; + +/* P.SR.F instruction pool */ +enum { + NM_SAVEF = 0x00, + NM_RESTOREF = 0x01, +}; + +/* P16.SYSCALL instruction pool */ +enum { + NM_SYSCALL16 = 0x00, + NM_HYPCALL16 = 0x01, +}; + +/* POOL16C_00 instruction pool */ +enum { + NM_NOT16 = 0x00, + NM_XOR16 = 0x01, + NM_AND16 = 0x02, + NM_OR16 = 0x03, +}; + +/* PP.LSX and PP.LSXS instruction pool */ +enum { + NM_LBX = 0x00, + NM_LHX = 0x04, + NM_LWX = 0x08, + NM_LDX = 0x0c, + + NM_SBX = 0x01, + NM_SHX = 0x05, + NM_SWX = 0x09, + NM_SDX = 0x0d, + + NM_LBUX = 0x02, + NM_LHUX = 0x06, + NM_LWC1X = 0x0a, + NM_LDC1X = 0x0e, + + NM_LWUX = 0x07, + NM_SWC1X = 0x0b, + NM_SDC1X = 0x0f, + + NM_LHXS = 0x04, + NM_LWXS = 0x08, + NM_LDXS = 0x0c, + + NM_SHXS = 0x05, + NM_SWXS = 0x09, + NM_SDXS = 0x0d, + + NM_LHUXS = 0x06, + NM_LWC1XS = 0x0a, + NM_LDC1XS = 0x0e, + + NM_LWUXS = 0x07, + NM_SWC1XS = 0x0b, + NM_SDC1XS = 0x0f, +}; + +/* ERETx instruction pool */ +enum { + NM_ERET = 0x00, + NM_ERETNC = 0x01, +}; + +/* POOL32FxF_{0, 1} insturction pool */ +enum { + NM_CFC1 = 0x40, + NM_CTC1 = 0x60, + NM_MFC1 = 0x80, + NM_MTC1 = 0xa0, + NM_MFHC1 = 0xc0, + NM_MTHC1 = 0xe0, + + NM_CVT_S_PL = 0x84, + NM_CVT_S_PU = 0xa4, + + NM_CVT_L_S = 0x004, + NM_CVT_L_D = 0x104, + NM_CVT_W_S = 0x024, + NM_CVT_W_D = 0x124, + + NM_RSQRT_S = 0x008, + NM_RSQRT_D = 0x108, + + NM_SQRT_S = 0x028, + NM_SQRT_D = 0x128, + + NM_RECIP_S = 0x048, + NM_RECIP_D = 0x148, + + NM_FLOOR_L_S = 0x00c, + NM_FLOOR_L_D = 0x10c, + + NM_FLOOR_W_S = 0x02c, + NM_FLOOR_W_D = 0x12c, + + NM_CEIL_L_S = 0x04c, + NM_CEIL_L_D = 0x14c, + NM_CEIL_W_S = 0x06c, + NM_CEIL_W_D = 0x16c, + NM_TRUNC_L_S = 0x08c, + NM_TRUNC_L_D = 0x18c, + NM_TRUNC_W_S = 0x0ac, + NM_TRUNC_W_D = 0x1ac, + NM_ROUND_L_S = 0x0cc, + NM_ROUND_L_D = 0x1cc, + NM_ROUND_W_S = 0x0ec, + NM_ROUND_W_D = 0x1ec, + + NM_MOV_S = 0x01, + NM_MOV_D = 0x81, + NM_ABS_S = 0x0d, + NM_ABS_D = 0x8d, + NM_NEG_S = 0x2d, + NM_NEG_D = 0xad, + NM_CVT_D_S = 0x04d, + NM_CVT_D_W = 0x0cd, + NM_CVT_D_L = 0x14d, + NM_CVT_S_D = 0x06d, + NM_CVT_S_W = 0x0ed, + NM_CVT_S_L = 0x16d, +}; + +/* P.LL instruction pool */ +enum { + NM_LL = 0x00, + NM_LLWP = 0x01, +}; + +/* P.SC instruction pool */ +enum { + NM_SC = 0x00, + NM_SCWP = 0x01, +}; + +/* P.DVP instruction pool */ +enum { + NM_DVP = 0x00, + NM_EVP = 0x01, +}; + /* SmartMIPS extension to MIPS32 */ #if defined(TARGET_MIPS64) From patchwork Thu Jul 19 12:54:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946329 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Wb1Q5QTdz9s7c for ; Thu, 19 Jul 2018 23:47:38 +1000 (AEST) Received: from localhost ([::1]:43060 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9HM-0001Fh-3s for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:47:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51046) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8WW-0003Mr-87 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:00:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8T9-0004Ex-HP for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:12 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:55280 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8T8-0004D2-Sh for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:55:43 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 78DF01A44FF; Thu, 19 Jul 2018 14:55:41 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 59FFD1A4156; Thu, 19 Jul 2018 14:55:41 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:35 +0200 Message-Id: <1532004912-13899-4-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 03/40] target/mips: Add nanoMIPS DSP ASE opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Stefan Markovic Add nanoMIPS opcodes for DSP ASE instruction pools and instructions. Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Richard Henderson --- target/mips/translate.c | 144 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 144 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 6a99a61..227b2c0 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16142,10 +16142,154 @@ enum { /* POOL32Axf instruction pool */ enum { + NM_POOL32AXF_1 = 0x01, + NM_POOL32AXF_2 = 0x02, NM_POOL32AXF_4 = 0x04, NM_POOL32AXF_5 = 0x05, + NM_POOL32AXF_7 = 0x07, }; +/* POOL32Axf_1 instruction pool */ +enum { + NM_POOL32AXF_1_0 = 0x00, + NM_POOL32AXF_1_1 = 0x01, + NM_POOL32AXF_1_3 = 0x03, + NM_POOL32AXF_1_4 = 0x04, + NM_POOL32AXF_1_5 = 0x05, + NM_POOL32AXF_1_7 = 0x07, +}; + +/* POOL32Axf_2 instruction pool */ +enum { + NM_POOL32AXF_2_0_7 = 0x00, + NM_POOL32AXF_2_8_15 = 0x01, + NM_POOL32AXF_2_16_23 = 0x02, + NM_POOL32AXF_2_24_31 = 0x03, +}; + +/* POOL32Axf_{4, 5} instruction pool */ +enum { + /* nanoMIPS DSP instructions */ + NM_ABSQ_S_QB = 0x00, + NM_ABSQ_S_PH = 0x08, + NM_ABSQ_S_W = 0x10, + NM_PRECEQ_W_PHL = 0x28, + NM_PRECEQ_W_PHR = 0x30, + NM_PRECEQU_PH_QBL = 0x38, + NM_PRECEQU_PH_QBR = 0x48, + NM_PRECEU_PH_QBL = 0x58, + NM_PRECEU_PH_QBR = 0x68, + NM_PRECEQU_PH_QBLA = 0x39, + NM_PRECEQU_PH_QBRA = 0x49, + NM_PRECEU_PH_QBLA = 0x59, + NM_PRECEU_PH_QBRA = 0x69, + NM_REPLV_PH = 0x01, + NM_REPLV_QB = 0x09, + NM_BITREV = 0x18, + NM_INSV = 0x20, + NM_RADDU_W_QB = 0x78, + + NM_BITSWAP = 0x05, + NM_WSBH = 0x3d, +}; + +/* POOL32Axf_7 instruction pool */ +enum { + NM_SHRA_R_QB = 0x0, + NM_SHRL_PH = 0x1, + NM_REPL_QB = 0x2, +}; + +/* POOL32Axf_1_0 instruction pool */ +enum { + NM_MFHI = 0x0, + NM_MFLO = 0x1, + NM_MTHI = 0x2, + NM_MTLO = 0x3, +}; + +/* POOL32Axf_1_1 instruction pool */ +enum { + NM_MTHLIP = 0x0, + NM_SHILOV = 0x1, +}; + +/* POOL32Axf_1_3 instruction pool */ +enum { + NM_RDDSP = 0x0, + NM_WRDSP = 0x1, + NM_EXTP = 0x2, + NM_EXTPDP = 0x3, +}; + +/* POOL32Axf_1_4 instruction pool */ +enum { + NM_SHLL_QB = 0x0, + NM_SHRL_QB = 0x1, +}; + +/* POOL32Axf_1_5 instruction pool */ +enum { + NM_MAQ_S_W_PHR = 0x0, + NM_MAQ_S_W_PHL = 0x1, + NM_MAQ_SA_W_PHR = 0x2, + NM_MAQ_SA_W_PHL = 0x3, +}; + +/* POOL32Axf_1_7 instruction pool */ +enum { + NM_EXTR_W = 0x0, + NM_EXTR_R_W = 0x1, + NM_EXTR_RS_W = 0x2, + NM_EXTR_S_H = 0x3, +}; + +/* POOL32Axf_2_0_7 instruction pool */ +enum { + NM_DPA_W_PH = 0x0, + NM_DPAQ_S_W_PH = 0x1, + NM_DPS_W_PH = 0x2, + NM_DPSQ_S_W_PH = 0x3, + NM_BALIGN = 0x4, + NM_MADD = 0x5, + NM_MULT = 0x6, + NM_EXTRV_W = 0x7, +}; + +/* POOL32Axf_2_8_15 instruction pool */ +enum { + NM_DPAX_W_PH = 0x0, + NM_DPAQ_SA_L_W = 0x1, + NM_DPSX_W_PH = 0x2, + NM_DPSQ_SA_L_W = 0x3, + NM_MADDU = 0x5, + NM_MULTU = 0x6, + NM_EXTRV_R_W = 0x7, +}; + +/* POOL32Axf_2_16_23 instruction pool */ +enum { + NM_DPAU_H_QBL = 0x0, + NM_DPAQX_S_W_PH = 0x1, + NM_DPSU_H_QBL = 0x2, + NM_DPSQX_S_W_PH = 0x3, + NM_EXTPV = 0x4, + NM_MSUB = 0x5, + NM_MULSA_W_PH = 0x6, + NM_EXTRV_RS_W = 0x7, +}; + +/* POOL32Axf_2_24_31 instruction pool */ +enum { + NM_DPAU_H_QBR = 0x0, + NM_DPAQX_SA_W_PH = 0x1, + NM_DPSU_H_QBR = 0x2, + NM_DPSQX_SA_W_PH = 0x3, + NM_EXTPDPV = 0x4, + NM_MSUBU = 0x5, + NM_MULSAQ_S_W_PH = 0x6, + NM_EXTRV_S_H = 0x7, +}; /* POOL32Axf_{4, 5} instruction pool */ enum { NM_CLO = 0x25, From patchwork Thu Jul 19 12:54:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946342 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Wb8n0c9Dz9s4r for ; Thu, 19 Jul 2018 23:53:59 +1000 (AEST) Received: from localhost ([::1]:43086 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9NU-0006eg-BC for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:53:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49974) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8W2-0003G5-JH for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:01:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8TG-0004KT-EX for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:58:42 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:55309 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8TG-0004Je-1S for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:55:50 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id A31F81A22AF; Thu, 19 Jul 2018 14:55:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 86C3F1A1D42; Thu, 19 Jul 2018 14:55:48 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:36 +0200 Message-Id: <1532004912-13899-5-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 04/40] target/mips: Add decode_nanomips_opc() function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Add empty body and invocation of decode_nanomips_opc() if the bit ISA_NANOMIPS32 is set in env->insn_flags. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 227b2c0..67a0f70 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16458,6 +16458,19 @@ enum { NM_EVP = 0x01, }; + +/* + * + * nanoMIPS decoding engine + * + */ + +static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) +{ + return 2; +} + + /* SmartMIPS extension to MIPS32 */ #if defined(TARGET_MIPS64) @@ -21263,8 +21276,13 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) insn_bytes = 4; decode_opc(env, ctx); } else if (ctx->insn_flags & ASE_MICROMIPS) { - ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next); - insn_bytes = decode_micromips_opc(env, ctx); + if (env->insn_flags & ISA_NANOMIPS32) { + ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next); + insn_bytes = decode_nanomips_opc(env, ctx); + } else { + ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next); + insn_bytes = decode_micromips_opc(env, ctx); + } } else if (ctx->insn_flags & ASE_MIPS16) { ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next); insn_bytes = decode_mips16_opc(env, ctx); From patchwork Thu Jul 19 12:54:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946336 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Wb5T24Hrz9s4r for ; Thu, 19 Jul 2018 23:51:09 +1000 (AEST) Received: from localhost ([::1]:43080 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9Kk-0004RG-TS for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:51:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48239) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8US-00033i-8A for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:00:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8TO-0004RW-6h for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:57:04 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56209 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8TN-0004QP-Qw for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:55:58 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 4CE2B1A4156; Thu, 19 Jul 2018 14:55:56 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 2EC801A1D42; Thu, 19 Jul 2018 14:55:56 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:37 +0200 Message-Id: <1532004912-13899-6-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 05/40] target/mips: Add nanoMIPS decoding and extraction utilities X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Add some basic utility functions and macros for nanoMIPS decoding engine. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Richard Henderson --- target/mips/translate.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 67a0f70..4e6ae1f 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16465,6 +16465,41 @@ enum { * */ +static int decode_gpr_gpr3(int r) +{ + static const int map[] = { 16, 17, 18, 19, 4, 5, 6, 7 }; + + return map[r & 0x7]; +} + +static int decode_gpr_gpr4(int r) +{ + static const int map[] = { 8, 9, 10, 11, 4, 5, 6, 7, + 16, 17, 18, 19, 20, 21, 22, 23 }; + + return map[r & 0xf]; +} + +/* Used for 16-bit store instructions. */ +static int decode_gpr_gpr4_zero(int r) +{ + static const int map[] = { 8, 9, 10, 0, 4, 5, 6, 7, + 16, 17, 18, 19, 20, 21, 22, 23 }; + + return map[r & 0xf]; +} + + +/* extraction utilities */ + +#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7) +#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7) +#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op) +#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7) +#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f) +#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f) + + static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) { return 2; From patchwork Thu Jul 19 12:54:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946335 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Wb5P2Pltz9s4r for ; Thu, 19 Jul 2018 23:51:05 +1000 (AEST) Received: from localhost ([::1]:43076 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9Kg-000491-U3 for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:51:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51308) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Wd-0003OG-Jf for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:00:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8TV-0004YK-2V for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:19 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56564 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8TU-0004WI-BF for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:56:04 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id CF3511A22AF; Thu, 19 Jul 2018 14:56:02 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id ADF811A1D42; Thu, 19 Jul 2018 14:56:02 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:38 +0200 Message-Id: <1532004912-13899-7-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 06/40] target/mips: Add emulation of misc nanoMIPS 16-bit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Add emulation of misc nanoMIPS 16-bit instructions from instruction pools P16, P16.BR, P16.BRI, P16.4X4 and other related pools. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 258 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 258 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 4e6ae1f..798f977 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16502,6 +16502,264 @@ static int decode_gpr_gpr4_zero(int r) static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) { + uint32_t op; + int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode)); + int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode)); + int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS1(ctx->opcode)); + + /* make sure instructions are on a halfword boundary */ + if (ctx->base.pc_next & 0x1) { + env->CP0_BadVAddr = ctx->base.pc_next; + generate_exception_end(ctx, EXCP_AdEL); + return 2; + } + + op = (ctx->opcode >> 10) & 0x3f; + switch (op) { + case NM_P16_MV: + { + int rt = NANOMIPS_EXTRACT_RD5(ctx->opcode); + if (rt != 0) { + /* MOVE */ + int rs = NANOMIPS_EXTRACT_RS5(ctx->opcode); + gen_arith(ctx, OPC_ADDU, rt, rs, 0); + } else { + /* P16.RI */ + switch ((ctx->opcode >> 3) & 0x3) { + case NM_P16_SYSCALL: + generate_exception_end(ctx, EXCP_SYSCALL); + break; + case NM_BREAK16: + generate_exception_end(ctx, EXCP_BREAK); + break; + case NM_SDBBP16: + if (is_uhi(extract32(ctx->opcode, 0, 3))) { + gen_helper_do_semihosting(cpu_env); + } else { + if (ctx->hflags & MIPS_HFLAG_SBRI) { + generate_exception_end(ctx, EXCP_RI); + } else { + generate_exception_end(ctx, EXCP_DBp); + } + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } + } + break; + case NM_P16_SHIFT: + { + int shift = (ctx->opcode) & 0x7; + uint32_t opc = 0; + shift = (shift == 0) ? 8 : shift; + + switch ((ctx->opcode >> 3) & 1) { + case NM_SLL16: + opc = OPC_SLL; + break; + case NM_SRL16: + opc = OPC_SRL; + break; + } + gen_shift_imm(ctx, opc, rt, rs, shift); + } + break; + case NM_P16C: + break; + case NM_P16_A1: + switch ((ctx->opcode >> 6) & 1) { + case NM_ADDIUR1SP: + gen_arith_imm(ctx, OPC_ADDIU, rt, 29, + extract32(ctx->opcode, 0, 6) << 2); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_P16_A2: + switch ((ctx->opcode >> 3) & 1) { + case NM_ADDIUR2: + { + uint8_t u = (uint8_t) extract32(ctx->opcode, 0, 3) << 2; + gen_arith_imm(ctx, OPC_ADDIU, rt, rs, u); + } + break; + case NM_P_ADDIURS5: + { + int rt = extract32(ctx->opcode, 5, 5); + if (rt != 0) { + int s = (sextract32(ctx->opcode, 4, 1) << 3) | + extract32(ctx->opcode, 0, 3); + /* s = sign_extend( s[3] . s[2:0] , from_nbits = 4)*/ + gen_arith_imm(ctx, OPC_ADDIU, rt, rt, s); + } + } + break; + } + break; + case NM_P16_ADDU: + switch (ctx->opcode & 0x1) { + case NM_ADDU16: + gen_arith(ctx, OPC_ADDU, rd, rs, rt); + break; + case NM_SUBU16: + gen_arith(ctx, OPC_SUBU, rd, rs, rt); + break; + } + break; + case NM_P16_4X4: + { + int rt = (extract32(ctx->opcode, 9, 1) << 3) | + extract32(ctx->opcode, 5, 3); + int rs = (extract32(ctx->opcode, 4, 1) << 3) | + extract32(ctx->opcode, 0, 3); + rt = decode_gpr_gpr4(rt); + rs = decode_gpr_gpr4(rs); + + switch (((ctx->opcode >> 7) & 0x2) | ((ctx->opcode >> 3) & 0x1)) { + case NM_ADDU4X4: + gen_arith(ctx, OPC_ADDU, rt, rs, rt); + break; + case NM_MUL4X4: + gen_r6_muldiv(ctx, R6_OPC_MUL, rt, rs, rt); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } + break; + case NM_LI16: + { + int imm = extract32(ctx->opcode, 0, 7); + imm = (imm == 0x7f ? -1 : imm); + if (rt != 0) { + tcg_gen_movi_tl(cpu_gpr[rt], imm); + } + } + break; + case NM_ANDI16: + { + uint32_t u = extract32(ctx->opcode, 0, 4); + u = (u == 12) ? 0xff : + (u == 13) ? 0xffff : u; + gen_logic_imm(ctx, OPC_ANDI, rt, rs, u); + } + break; + case NM_P16_LB: + break; + case NM_P16_LH: + break; + case NM_LW16: + break; + case NM_LWSP16: + break; + case NM_LW4X4: + break; + case NM_SW4X4: + break; + case NM_LWGP16: + break; + case NM_SWSP16: + break; + case NM_SW16: + break; + case NM_SWGP16: + break; + case NM_BC16: + gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, + (sextract32(ctx->opcode, 0, 1) << 10) | + (extract32(ctx->opcode, 1, 9) << 1), + 0); + break; + case NM_BALC16: + gen_compute_branch(ctx, OPC_BGEZAL, 2, 0, 0, + (sextract32(ctx->opcode, 0, 1) << 10) | + (extract32(ctx->opcode, 1, 9) << 1), + 0); + break; + case NM_BEQZC16: + case NM_BNEZC16: + gen_compute_branch(ctx, op == NM_BNEZC16 ? OPC_BNE : OPC_BEQ, 2, + rt, 0, + (sextract32(ctx->opcode, 0, 1) << 7) | + (extract32(ctx->opcode, 1, 6) << 1), + 0); + break; + case NM_P16_BR: + switch (ctx->opcode & 0xf) { + case 0: + /* P16.JRC */ + switch ((ctx->opcode >> 4) & 1) { + case NM_JRC: + gen_compute_branch(ctx, OPC_JR, 2, + extract32(ctx->opcode, 5, 5), 0, 0, 0); + break; + case NM_JALRC16: + gen_compute_branch(ctx, OPC_JALR, 2, + extract32(ctx->opcode, 5, 5), 31, 0, 0); + break; + } + break; + default: + /* P16.BRI */ + if (extract32(ctx->opcode, 4, 3) < extract32(ctx->opcode, 7, 3)) { + /* BEQC16 */ + gen_compute_branch(ctx, OPC_BEQ, 2, rs, rt, + extract32(ctx->opcode, 0, 4) << 1, 0); + } else { + /* BNEC16 */ + gen_compute_branch(ctx, OPC_BNE, 2, rs, rt, + extract32(ctx->opcode, 0, 4) << 1, 0); + } + break; + } + break; + case NM_P16_SR: + break; + case NM_MOVEP: + case NM_MOVEPREV: + { + static const int gpr2reg1[] = {4, 5, 6, 7}; + static const int gpr2reg2[] = {5, 6, 7, 8}; + int re; + int rd2 = extract32(ctx->opcode, 3, 1) << 1 | + extract32(ctx->opcode, 8, 1); + int r1 = gpr2reg1[rd2]; + int r2 = gpr2reg2[rd2]; + int r3 = extract32(ctx->opcode, 4, 1) << 3 | + extract32(ctx->opcode, 0, 3); + int r4 = extract32(ctx->opcode, 9, 1) << 3 | + extract32(ctx->opcode, 5, 3); + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + if (op == NM_MOVEP) { + rd = r1; + re = r2; + rs = decode_gpr_gpr4_zero(r3); + rt = decode_gpr_gpr4_zero(r4); + } else { + rd = decode_gpr_gpr4(r3); + re = decode_gpr_gpr4(r4); + rs = r1; + rt = r2; + } + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + tcg_gen_mov_tl(cpu_gpr[rd], t0); + tcg_gen_mov_tl(cpu_gpr[re], t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + default: + break; + } + return 2; } From patchwork Thu Jul 19 12:54:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946325 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WZxt0T58z9s7c for ; Thu, 19 Jul 2018 23:44:34 +1000 (AEST) Received: from localhost ([::1]:43042 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9EN-0006zJ-HE for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:44:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50694) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8WM-0003JS-7X for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:00:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Tb-0004g7-Ne for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:02 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56653 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8Tb-0004dy-1y for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:56:11 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 813F31A416D; Thu, 19 Jul 2018 14:56:09 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 63DC51A1D42; Thu, 19 Jul 2018 14:56:09 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:39 +0200 Message-Id: <1532004912-13899-8-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 07/40] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Add emulation of LWXS16, LB16, SB16, LBU16, LH16, SH16, LHU16, LW16, LWSP16, LW4X4, SW4X4, LWGP16, SWSP16, SW16, and SWGP16 instructions. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 114 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 798f977..1a839be 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16472,6 +16472,14 @@ static int decode_gpr_gpr3(int r) return map[r & 0x7]; } +/* Used for 16-bit store instructions. */ +static int decode_gpr_gpr3_src_store(int r) +{ + static const int map[] = { 0, 17, 18, 19, 4, 5, 6, 7 }; + + return map[r & 0x7]; +} + static int decode_gpr_gpr4(int r) { static const int map[] = { 8, 9, 10, 11, 4, 5, 6, 7, @@ -16568,6 +16576,13 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) } break; case NM_P16C: + switch (ctx->opcode & 1) { + case NM_POOL16C_0: + break; + case NM_LWXS16: + gen_ldxs(ctx, rt, rs, rd); + break; + } break; case NM_P16_A1: switch ((ctx->opcode >> 6) & 1) { @@ -16651,24 +16666,123 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) } break; case NM_P16_LB: + { + uint32_t u = extract32(ctx->opcode, 0, 2); + switch (((ctx->opcode) >> 2) & 0x03) { + case NM_LB16: + gen_ld(ctx, OPC_LB, rt, rs, u); + break; + case NM_SB16: + { + int rt = decode_gpr_gpr3_src_store( + NANOMIPS_EXTRACT_RD(ctx->opcode)); + gen_st(ctx, OPC_SB, rt, rs, u); + } + break; + case NM_LBU16: + gen_ld(ctx, OPC_LBU, rt, rs, u); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_P16_LH: + { + uint32_t u = extract32(ctx->opcode, 1, 2) << 1; + switch ((((ctx->opcode >> 3) & 1) << 1) | (ctx->opcode & 1)) { + case NM_LH16: + gen_ld(ctx, OPC_LH, rt, rs, u); + break; + case NM_SH16: + { + int rt = decode_gpr_gpr3_src_store( + NANOMIPS_EXTRACT_RD(ctx->opcode)); + gen_st(ctx, OPC_SH, rt, rs, u); + } + break; + case NM_LHU16: + gen_ld(ctx, OPC_LHU, rt, rs, u); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_LW16: + { + int u = extract32(ctx->opcode, 0, 4) << 2; + gen_ld(ctx, OPC_LW, rt, rs, u); + } break; case NM_LWSP16: + { + int rt = NANOMIPS_EXTRACT_RD5(ctx->opcode); + int u = extract32(ctx->opcode, 0, 5) << 2; + + gen_ld(ctx, OPC_LW, rt, 29, u); + } break; case NM_LW4X4: + { + int rt = (extract32(ctx->opcode, 9, 1) << 3) | + extract32(ctx->opcode, 5, 3); + int rs = (extract32(ctx->opcode, 4, 1) << 3) | + extract32(ctx->opcode, 0, 3); + int u = (extract32(ctx->opcode, 3, 1) << 3) | + (extract32(ctx->opcode, 8, 1) << 2); + rt = decode_gpr_gpr4(rt); + rs = decode_gpr_gpr4(rs); + gen_ld(ctx, OPC_LW, rt, rs, u); + } break; case NM_SW4X4: + { + int rt = (extract32(ctx->opcode, 9, 1) << 3) | + extract32(ctx->opcode, 5, 3); + int rs = (extract32(ctx->opcode, 4, 1) << 3) | + extract32(ctx->opcode, 0, 3); + int u = (extract32(ctx->opcode, 3, 1) << 3) | + (extract32(ctx->opcode, 8, 1) << 2); + rt = decode_gpr_gpr4_zero(rt); + rs = decode_gpr_gpr4(rs); + gen_st(ctx, OPC_SW, rt, rs, u); + } break; case NM_LWGP16: + { + int u = extract32(ctx->opcode, 0, 7) << 2; + gen_ld(ctx, OPC_LW, rt, 28, u); + } break; case NM_SWSP16: + { + int rt = NANOMIPS_EXTRACT_RD5(ctx->opcode); + int u = extract32(ctx->opcode, 0, 5) << 2; + + gen_st(ctx, OPC_SW, rt, 29, u); + } break; case NM_SW16: + { + int rt = decode_gpr_gpr3_src_store( + NANOMIPS_EXTRACT_RD(ctx->opcode)); + int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode)); + int u = extract32(ctx->opcode, 0, 4) << 2; + + gen_st(ctx, OPC_SW, rt, rs, u); + } break; case NM_SWGP16: + { + int rt = decode_gpr_gpr3_src_store( + NANOMIPS_EXTRACT_RD(ctx->opcode)); + int u = extract32(ctx->opcode, 0, 7) << 2; + + gen_st(ctx, OPC_SW, rt, 28, u); + } break; case NM_BC16: gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, From patchwork Thu Jul 19 12:54:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946357 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbDP2xHlz9s4r for ; Thu, 19 Jul 2018 23:57:09 +1000 (AEST) Received: from localhost ([::1]:43110 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9QZ-0001FM-1T for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:57:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48511) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Up-000366-TK for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:00:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Tl-0004rq-Qa for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:57:27 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56729 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8Tl-0004po-6s for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:56:21 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B68961A22AF; Thu, 19 Jul 2018 14:56:19 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 9A4B81A1D42; Thu, 19 Jul 2018 14:56:19 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:40 +0200 Message-Id: <1532004912-13899-9-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 08/40] target/mips: Add emulation of nanoMIPS 16-bit logic instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Add emulation of NOT16, AND16, XOR16, OR16 instructions. Reviewed-by: Richard Henderson Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 1a839be..12505a8 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16508,6 +16508,27 @@ static int decode_gpr_gpr4_zero(int r) #define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f) +static void gen_pool16c_nanomips_insn(DisasContext *ctx) +{ + int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode)); + int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode)); + + switch ((ctx->opcode >> 2) & 0x3) { + case NM_NOT16: + gen_logic(ctx, OPC_NOR, rt, rs, 0); + break; + case NM_AND16: + gen_logic(ctx, OPC_AND, rt, rt, rs); + break; + case NM_XOR16: + gen_logic(ctx, OPC_XOR, rt, rt, rs); + break; + case NM_OR16: + gen_logic(ctx, OPC_OR, rt, rt, rs); + break; + } +} + static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) { uint32_t op; @@ -16578,6 +16599,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) case NM_P16C: switch (ctx->opcode & 1) { case NM_POOL16C_0: + gen_pool16c_nanomips_insn(ctx); break; case NM_LWXS16: gen_ldxs(ctx, rt, rs, rd); From patchwork Thu Jul 19 12:54:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946354 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbD6371Zz9s4r for ; Thu, 19 Jul 2018 23:56:54 +1000 (AEST) Received: from localhost ([::1]:43104 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9QK-00012m-3Q for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:56:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48653) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8V2-00038u-NC for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:01:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Ty-00058E-Om for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:57:40 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56800 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8Ty-00055V-1a for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:56:34 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 3BFF51A22AF; Thu, 19 Jul 2018 14:56:32 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 1F08E1A1D42; Thu, 19 Jul 2018 14:56:32 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:41 +0200 Message-Id: <1532004912-13899-10-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 09/40] target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Add emulation of SAVE16 and RESTORE.JRC16 instructions. Routines gen_save(), gen_restore(), and gen_adjust_sp() are provided for this purpose. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Richard Henderson --- target/mips/translate.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 12505a8..2237597 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16508,6 +16508,65 @@ static int decode_gpr_gpr4_zero(int r) #define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f) +static void gen_adjust_sp(DisasContext *ctx, int u) +{ + TCGv tsp = tcg_temp_new(); + gen_base_offset_addr(ctx, tsp, 29, u); + gen_store_gpr(tsp, 29); + tcg_temp_free(tsp); +} + +static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count, + uint8_t gp, uint16_t u) +{ + int counter = 0; + TCGv va = tcg_temp_new(); + TCGv t0 = tcg_temp_new(); + + while (counter != count) { + bool use_gp = gp && (counter == count - 1); + int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f); + int this_offset = -((counter + 1) << 2); + gen_base_offset_addr(ctx, va, 29, this_offset); + gen_load_gpr(t0, this_rt); + tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx, + (MO_TEUL | ctx->default_tcg_memop_mask)); + counter++; + } + + /* adjust stack pointer */ + gen_adjust_sp(ctx, -u); + + tcg_temp_free(t0); + tcg_temp_free(va); +} + +static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count, + uint8_t gp, uint16_t u) +{ + int counter = 0; + TCGv va = tcg_temp_new(); + TCGv t0 = tcg_temp_new(); + + while (counter != count) { + bool use_gp = gp && (counter == count - 1); + int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f); + int this_offset = u - ((counter + 1) << 2); + gen_base_offset_addr(ctx, va, 29, this_offset); + tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TESL | + ctx->default_tcg_memop_mask); + tcg_gen_ext32s_tl(t0, t0); + gen_store_gpr(t0, this_rt); + counter++; + } + + /* adjust stack pointer */ + gen_adjust_sp(ctx, u); + + tcg_temp_free(t0); + tcg_temp_free(va); +} + static void gen_pool16c_nanomips_insn(DisasContext *ctx) { int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode)); @@ -16856,6 +16915,20 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) } break; case NM_P16_SR: + { + int count = extract32(ctx->opcode, 0, 4); + int u = extract32(ctx->opcode, 4, 4) << 4; + int rt = 30 + ((ctx->opcode >> 9) & 1); + switch ((ctx->opcode >> 8) & 1) { + case NM_SAVE16: + gen_save(ctx, rt, count, 0, u); + break; + case NM_RESTORE_JRC16: + gen_restore(ctx, rt, count, 0, u); + gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0); + break; + } + } break; case NM_MOVEP: case NM_MOVEPREV: From patchwork Thu Jul 19 12:54:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946382 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbRy6yN0z9s4r for ; Fri, 20 Jul 2018 00:07:10 +1000 (AEST) Received: from localhost ([::1]:43235 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9aG-0001fF-H9 for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:07:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52441) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8XA-0003ZG-3n for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:04:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8U5-0005GJ-Lg for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:52 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56851 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8U4-0005Dd-Sx for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:56:41 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 660201A4156; Thu, 19 Jul 2018 14:56:39 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 481FD1A1D42; Thu, 19 Jul 2018 14:56:39 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:42 +0200 Message-Id: <1532004912-13899-11-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 10/40] target/mips: Add emulation of some common nanoMIPS 32-bit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Add emulation of SIGRIE, SYSCALL, BREAK, SDBBP, ADDIU, ADDIUPC, ADDIUGP.W, LWGP, SWGP, ORI, XORI, ANDI, and other instructions. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic --- target/mips/translate.c | 285 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 284 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 2237597..201baf1 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16588,6 +16588,289 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx) } } +static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) +{ + uint16_t insn; + int rt, rs; + uint32_t op; + + insn = cpu_lduw_code(env, ctx->base.pc_next + 2); + ctx->opcode = (ctx->opcode << 16) | insn; + + rt = (ctx->opcode >> 21) & 0x1f; + rs = (ctx->opcode >> 16) & 0x1f; + + op = (ctx->opcode >> 26) & 0x3f; + switch (op) { + case NM_P_ADDIU: + if (rt == 0) { + /* P.RI */ + switch ((ctx->opcode >> 19) & 0x03) { + case NM_SIGRIE: + default: + generate_exception_end(ctx, EXCP_RI); + break; + case NM_P_SYSCALL: + if (((ctx->opcode >> 18) & 0x01) == NM_SYSCALL) { + generate_exception_end(ctx, EXCP_SYSCALL); + } else { + generate_exception_end(ctx, EXCP_RI); + } + break; + case NM_BREAK: + generate_exception_end(ctx, EXCP_BREAK); + break; + case NM_SDBBP: + if (is_uhi(extract32(ctx->opcode, 0, 19))) { + gen_helper_do_semihosting(cpu_env); + } else { + if (ctx->hflags & MIPS_HFLAG_SBRI) { + generate_exception_end(ctx, EXCP_RI); + } else { + generate_exception_end(ctx, EXCP_DBp); + } + } + break; + } + } else { + uint16_t imm; + imm = (uint16_t) extract32(ctx->opcode, 0, 16); + if (rs != 0) { + tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } else { + tcg_gen_movi_tl(cpu_gpr[rt], imm); + } + } + break; + case NM_ADDIUPC: + if (rt != 0) { + int32_t offset = sextract32(ctx->opcode, 0, 1) << 21 + | extract32(ctx->opcode, 1, 20) << 1; + target_long addr = addr_add(ctx, ctx->base.pc_next + 4, offset); + tcg_gen_movi_tl(cpu_gpr[rt], addr); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } + break; + case NM_POOL32A: + break; + case NM_P_GP_W: + switch (ctx->opcode & 0x03) { + case NM_ADDIUGP_W: + if (rt != 0) { + uint32_t offset = extract32(ctx->opcode, 0, 21); + if (offset == 0) { + gen_load_gpr(cpu_gpr[rt], 28); + } else { + TCGv t0; + t0 = tcg_temp_new(); + tcg_gen_movi_tl(t0, offset); + gen_op_addr_add(ctx, cpu_gpr[rt], cpu_gpr[28], t0); + tcg_temp_free(t0); + } + } + break; + case NM_LWGP: + gen_ld(ctx, OPC_LW, rt, 28, extract32(ctx->opcode, 2, 19) << 2); + break; + case NM_SWGP: + gen_st(ctx, OPC_SW, rt, 28, extract32(ctx->opcode, 2, 19) << 2); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_P48I: + return 6; + case NM_P_U12: + switch ((ctx->opcode >> 12) & 0x0f) { + case NM_ORI: + gen_logic_imm(ctx, OPC_ORI, rt, rs, extract32(ctx->opcode, 0, 12)); + break; + case NM_XORI: + gen_logic_imm(ctx, OPC_XORI, rt, rs, extract32(ctx->opcode, 0, 12)); + break; + case NM_ANDI: + gen_logic_imm(ctx, OPC_ANDI, rt, rs, extract32(ctx->opcode, 0, 12)); + break; + case NM_P_SR: + switch ((ctx->opcode >> 20) & 1) { + case NM_PP_SR: + switch (ctx->opcode & 3) { + case NM_SAVE: + gen_save(ctx, rt, extract32(ctx->opcode, 16, 4), + (ctx->opcode >> 2) & 1, + extract32(ctx->opcode, 3, 9) << 3); + break; + case NM_RESTORE: + case NM_RESTORE_JRC: + gen_restore(ctx, rt, extract32(ctx->opcode, 16, 4), + (ctx->opcode >> 2) & 1, + extract32(ctx->opcode, 3, 9) << 3); + if ((ctx->opcode & 3) == NM_RESTORE_JRC) { + gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0); + } + break; + } + break; + case NM_P_SR_F: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_SLTI: + gen_slt_imm(ctx, OPC_SLTI, rt, rs, extract32(ctx->opcode, 0, 12)); + break; + case NM_SLTIU: + gen_slt_imm(ctx, OPC_SLTIU, rt, rs, extract32(ctx->opcode, 0, 12)); + break; + case NM_SEQI: + { + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_local_new(); + TCGLabel *l1 = gen_new_label(); + + gen_load_gpr(t0, rs); + tcg_gen_movi_tl(t1, extract32(ctx->opcode, 0, 12)); + tcg_gen_movi_tl(t2, 0); + tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1); + tcg_gen_movi_tl(t2, 1); + gen_set_label(l1); + gen_store_gpr(t2, rt); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + } + break; + case NM_ADDIUNEG: + { + int16_t imm; + imm = (int16_t) extract32(ctx->opcode, 0, 12); + gen_arith_imm(ctx, OPC_ADDIU, rt, rs, -imm); + } + break; + case NM_P_SHIFT: + { + int shift = extract32(ctx->opcode, 0, 5); + switch ((ctx->opcode >> 5) & 0x0f) { + case NM_P_SLL: + if (rt == 0 && shift == 0) { + /* NOP */ + } else if (rt == 0 && shift == 3) { + /* EHB treat as NOP */ + } else if (rt == 0 && shift == 5) { + /* PAUSE */ + if (ctx->hflags & MIPS_HFLAG_BMASK) { + generate_exception_end(ctx, EXCP_RI); + } + } else if (rt == 0 && shift == 6) { + /* SYNC */ + check_insn(ctx, ISA_MIPS2); + /* Treat as NOP. */ + } else { + /* SLL */ + gen_shift_imm(ctx, OPC_SLL, rt, rs, + extract32(ctx->opcode, 0, 5)); + } + break; + case NM_SRL: + gen_shift_imm(ctx, OPC_SRL, rt, rs, + extract32(ctx->opcode, 0, 5)); + break; + case NM_SRA: + gen_shift_imm(ctx, OPC_SRA, rt, rs, + extract32(ctx->opcode, 0, 5)); + break; + case NM_ROTR: + gen_shift_imm(ctx, OPC_ROTR, rt, rs, + extract32(ctx->opcode, 0, 5)); + break; + } + } + break; + case NM_P_ROTX: + break; + case NM_P_INS: + switch (((ctx->opcode >> 10) & 2) | ((ctx->opcode >> 5) & 1)) { + case NM_INS: + gen_bitops(ctx, OPC_INS, rt, rs, extract32(ctx->opcode, 0, 5), + extract32(ctx->opcode, 6, 5)); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_P_EXT: + switch (((ctx->opcode >> 10) & 2) | ((ctx->opcode >> 5) & 1)) { + case NM_EXT: + gen_bitops(ctx, OPC_EXT, rt, rs, extract32(ctx->opcode, 0, 5), + extract32(ctx->opcode, 6, 5)); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_POOL32F: + break; + case NM_POOL32S: + break; + case NM_P_LUI: + switch ((ctx->opcode >> 1) & 1) { + case NM_LUI: + if (rt != 0) { + tcg_gen_movi_tl(cpu_gpr[rt], + sextract32(ctx->opcode, 0, 1) << 31 | + extract32(ctx->opcode, 2, 10) << 21 | + extract32(ctx->opcode, 12, 9) << 12); + } + break; + case NM_ALUIPC: + if (rt != 0) { + int offset = sextract32(ctx->opcode, 0, 1) << 31 | + extract32(ctx->opcode, 2, 10) << 21 | + extract32(ctx->opcode, 12, 9) << 12; + target_long addr; + addr = ~0xFFF & addr_add(ctx, ctx->base.pc_next + 4, offset); + tcg_gen_movi_tl(cpu_gpr[rt], addr); + } + break; + } + break; + case NM_P_GP_BH: + break; + case NM_P_LS_U12: + break; + case NM_P_LS_S9: + break; + case NM_MOVE_BALC: + break; + case NM_P_BAL: + break; + case NM_P_J: + break; + case NM_P_BR1: + break; + case NM_P_BR2: + break; + case NM_P_BRI: + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + return 4; +} + static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) { uint32_t op; @@ -16966,7 +17249,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) } break; default: - break; + return decode_nanomips_32_48_opc(env, ctx); } return 2; From patchwork Thu Jul 19 12:54:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946316 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WZqP43q8z9s7c for ; Thu, 19 Jul 2018 23:38:57 +1000 (AEST) Received: from localhost ([::1]:43012 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg98x-0001st-3O for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:38:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48819) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8VG-00039f-S2 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8UC-0005N5-Q1 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:57:54 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56879 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8UC-0005LM-67 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:56:48 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 9659E1A22AF; Thu, 19 Jul 2018 14:56:46 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 78F7F1A1D42; Thu, 19 Jul 2018 14:56:46 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:43 +0200 Message-Id: <1532004912-13899-12-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:09 -0400 Subject: [Qemu-devel] [PATCH v3 11/40] target/mips: Add emulation of nanoMIPS 48-bit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Add emulation of LI48, ADDIU48, ADDIUGP48, ADDIUPC48, LWPC48, and SWPC48 instructions. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic --- target/mips/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 201baf1..c47ee7d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16682,6 +16682,72 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } break; case NM_P48I: + insn = cpu_lduw_code(env, ctx->base.pc_next + 4); + switch ((ctx->opcode >> 16) & 0x1f) { + case NM_LI48: + if (rt != 0) { + tcg_gen_movi_tl(cpu_gpr[rt], + extract32(ctx->opcode, 0, 16) | insn << 16); + } + break; + case NM_ADDIU48: + if (rt != 0) { + tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rt], + extract32(ctx->opcode, 0, 16) | insn << 16); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } + break; + case NM_ADDIUGP48: + if (rt != 0) { + tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[28], + extract32(ctx->opcode, 0, 16) | insn << 16); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } + break; + case NM_ADDIUPC48: + if (rt != 0) { + int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16; + target_long addr = addr_add(ctx, ctx->base.pc_next + 6, offset); + + tcg_gen_movi_tl(cpu_gpr[rt], addr); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } + break; + case NM_LWPC48: + if (rt != 0) { + TCGv t0; + t0 = tcg_temp_new(); + + int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16; + target_long addr = addr_add(ctx, ctx->base.pc_next + 6, offset); + + tcg_gen_movi_tl(t0, addr); + tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_TESL); + tcg_temp_free(t0); + } + break; + case NM_SWPC48: + { + TCGv t0, t1; + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + + int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16; + target_long addr = addr_add(ctx, ctx->base.pc_next + 6, offset); + + tcg_gen_movi_tl(t0, addr); + gen_load_gpr(t1, rt); + + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); + + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } return 6; case NM_P_U12: switch ((ctx->opcode >> 12) & 0x0f) { From patchwork Thu Jul 19 12:54:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946322 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WZtp02QNz9s5c for ; Thu, 19 Jul 2018 23:41:53 +1000 (AEST) Received: from localhost ([::1]:43032 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9Bn-0004kj-HE for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:41:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48928) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8VO-0003A9-4L for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8UK-0005VV-37 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:58:02 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56900 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8UJ-0005TB-DL for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:56:55 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id DA94F1A4156; Thu, 19 Jul 2018 14:56:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id BD6921A1D42; Thu, 19 Jul 2018 14:56:53 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:44 +0200 Message-Id: <1532004912-13899-13-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:09 -0400 Subject: [Qemu-devel] [PATCH v3 12/40] target/mips: Add emulation of nanoMIPS FP instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Add emulation of basic floating point arithmetic for nanoMIPS. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic Reviewed-by: Richard Henderson --- target/mips/translate.c | 300 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 300 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index c47ee7d..2c7f62e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16588,6 +16588,305 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx) } } +static void gen_pool32f_nanomips_insn(DisasContext *ctx) +{ + int rt, rs, rd; + + rt = (ctx->opcode >> 21) & 0x1f; + rs = (ctx->opcode >> 16) & 0x1f; + rd = (ctx->opcode >> 11) & 0x1f; + + if (!(ctx->CP0_Config1 & (1 << CP0C1_FP))) { + generate_exception_end(ctx, EXCP_RI); + return; + } + check_cp1_enabled(ctx); + switch (ctx->opcode & 0x07) { + case NM_POOL32F_0: + switch ((ctx->opcode >> 3) & 0x7f) { + case NM_RINT_S: + gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0); + break; + case NM_RINT_D: + gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0); + break; + case NM_CLASS_S: + gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0); + break; + case NM_CLASS_D: + gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0); + break; + case NM_ADD_S: + gen_farith(ctx, OPC_ADD_S, rt, rs, rd, 0); + break; + case NM_ADD_D: + gen_farith(ctx, OPC_ADD_D, rt, rs, rd, 0); + break; + case NM_SUB_S: + gen_farith(ctx, OPC_SUB_S, rt, rs, rd, 0); + break; + case NM_SUB_D: + gen_farith(ctx, OPC_SUB_D, rt, rs, rd, 0); + break; + case NM_MUL_S: + gen_farith(ctx, OPC_MUL_S, rt, rs, rd, 0); + break; + case NM_MUL_D: + gen_farith(ctx, OPC_MUL_D, rt, rs, rd, 0); + break; + case NM_DIV_S: + gen_farith(ctx, OPC_DIV_S, rt, rs, rd, 0); + break; + case NM_DIV_D: + gen_farith(ctx, OPC_DIV_D, rt, rs, rd, 0); + break; + case NM_SELEQZ_S: + gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs); + break; + case NM_SELEQZ_D: + gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs); + break; + case NM_SELNEZ_S: + gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs); + break; + case NM_SELNEZ_D: + gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs); + break; + case NM_SEL_S: + gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs); + break; + case NM_SEL_D: + gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs); + break; + case NM_MADDF_S: + gen_farith(ctx, OPC_MADDF_S, rt, rs, rd, 0); + break; + case NM_MADDF_D: + gen_farith(ctx, OPC_MADDF_D, rt, rs, rd, 0); + break; + case NM_MSUBF_S: + gen_farith(ctx, OPC_MSUBF_S, rt, rs, rd, 0); + break; + case NM_MSUBF_D: + gen_farith(ctx, OPC_MSUBF_D, rt, rs, rd, 0); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_POOL32F_3: + switch ((ctx->opcode >> 3) & 0x07) { + case NM_MIN_FMT: + switch ((ctx->opcode >> 9) & 1) { + case FMT_SDPS_S: + gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0); + break; + case FMT_SDPS_D: + gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0); + break; + } + break; + case NM_MAX_FMT: + switch ((ctx->opcode >> 9) & 1) { + case FMT_SDPS_S: + gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0); + break; + case FMT_SDPS_D: + gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0); + break; + } + break; + case NM_MINA_FMT: + switch ((ctx->opcode >> 9) & 1) { + case FMT_SDPS_S: + gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0); + break; + case FMT_SDPS_D: + gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0); + break; + } + break; + case NM_MAXA_FMT: + switch ((ctx->opcode >> 9) & 1) { + case FMT_SDPS_S: + gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0); + break; + case FMT_SDPS_D: + gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0); + break; + } + break; + case NM_POOL32FXF: + switch ((ctx->opcode >> 6) & 0xff) { + case NM_CFC1: + gen_cp1(ctx, OPC_CFC1, rt, rs); + break; + case NM_CTC1: + gen_cp1(ctx, OPC_CTC1, rt, rs); + break; + case NM_MFC1: + gen_cp1(ctx, OPC_MFC1, rt, rs); + break; + case NM_MTC1: + gen_cp1(ctx, OPC_MTC1, rt, rs); + break; + case NM_MFHC1: + gen_cp1(ctx, OPC_MFHC1, rt, rs); + break; + case NM_MTHC1: + gen_cp1(ctx, OPC_MTHC1, rt, rs); + break; + case NM_CVT_S_PL: + gen_farith(ctx, OPC_CVT_S_PL, -1, rs, rt, 0); + break; + case NM_CVT_S_PU: + gen_farith(ctx, OPC_CVT_S_PU, -1, rs, rt, 0); + break; + default: + switch ((ctx->opcode >> 6) & 0x1ff) { + case NM_CVT_L_S: + gen_farith(ctx, OPC_CVT_L_S, -1, rs, rt, 0); + break; + case NM_CVT_L_D: + gen_farith(ctx, OPC_CVT_L_D, -1, rs, rt, 0); + break; + case NM_CVT_W_S: + gen_farith(ctx, OPC_CVT_W_S, -1, rs, rt, 0); + break; + case NM_CVT_W_D: + gen_farith(ctx, OPC_CVT_W_D, -1, rs, rt, 0); + break; + case NM_RSQRT_S: + gen_farith(ctx, OPC_RSQRT_S, -1, rs, rt, 0); + break; + case NM_RSQRT_D: + gen_farith(ctx, OPC_RSQRT_D, -1, rs, rt, 0); + break; + case NM_SQRT_S: + gen_farith(ctx, OPC_SQRT_S, -1, rs, rt, 0); + break; + case NM_SQRT_D: + gen_farith(ctx, OPC_SQRT_D, -1, rs, rt, 0); + break; + case NM_RECIP_S: + gen_farith(ctx, OPC_RECIP_S, -1, rs, rt, 0); + break; + case NM_RECIP_D: + gen_farith(ctx, OPC_RECIP_D, -1, rs, rt, 0); + break; + case NM_FLOOR_L_S: + gen_farith(ctx, OPC_FLOOR_L_S, -1, rs, rt, 0); + break; + case NM_FLOOR_L_D: + gen_farith(ctx, OPC_FLOOR_L_D, -1, rs, rt, 0); + break; + case NM_FLOOR_W_S: + gen_farith(ctx, OPC_FLOOR_W_S, -1, rs, rt, 0); + break; + case NM_FLOOR_W_D: + gen_farith(ctx, OPC_FLOOR_W_D, -1, rs, rt, 0); + break; + case NM_CEIL_L_S: + gen_farith(ctx, OPC_CEIL_L_S, -1, rs, rt, 0); + break; + case NM_CEIL_L_D: + gen_farith(ctx, OPC_CEIL_L_D, -1, rs, rt, 0); + break; + case NM_CEIL_W_S: + gen_farith(ctx, OPC_CEIL_W_S, -1, rs, rt, 0); + break; + case NM_CEIL_W_D: + gen_farith(ctx, OPC_CEIL_W_D, -1, rs, rt, 0); + break; + case NM_TRUNC_L_S: + gen_farith(ctx, OPC_TRUNC_L_S, -1, rs, rt, 0); + break; + case NM_TRUNC_L_D: + gen_farith(ctx, OPC_TRUNC_L_D, -1, rs, rt, 0); + break; + case NM_TRUNC_W_S: + gen_farith(ctx, OPC_TRUNC_W_S, -1, rs, rt, 0); + break; + case NM_TRUNC_W_D: + gen_farith(ctx, OPC_TRUNC_W_D, -1, rs, rt, 0); + break; + case NM_ROUND_L_S: + gen_farith(ctx, OPC_ROUND_L_S, -1, rs, rt, 0); + break; + case NM_ROUND_L_D: + gen_farith(ctx, OPC_ROUND_L_D, -1, rs, rt, 0); + break; + case NM_ROUND_W_S: + gen_farith(ctx, OPC_ROUND_W_S, -1, rs, rt, 0); + break; + case NM_ROUND_W_D: + gen_farith(ctx, OPC_ROUND_W_D, -1, rs, rt, 0); + break; + case NM_MOV_S: + gen_farith(ctx, OPC_MOV_S, -1, rs, rt, 0); + break; + case NM_MOV_D: + gen_farith(ctx, OPC_MOV_D, -1, rs, rt, 0); + break; + case NM_ABS_S: + gen_farith(ctx, OPC_ABS_S, -1, rs, rt, 0); + break; + case NM_ABS_D: + gen_farith(ctx, OPC_ABS_D, -1, rs, rt, 0); + break; + case NM_NEG_S: + gen_farith(ctx, OPC_NEG_S, -1, rs, rt, 0); + break; + case NM_NEG_D: + gen_farith(ctx, OPC_NEG_D, -1, rs, rt, 0); + break; + case NM_CVT_D_S: + gen_farith(ctx, OPC_CVT_D_S, -1, rs, rt, 0); + break; + case NM_CVT_D_W: + gen_farith(ctx, OPC_CVT_D_W, -1, rs, rt, 0); + break; + case NM_CVT_D_L: + gen_farith(ctx, OPC_CVT_D_L, -1, rs, rt, 0); + break; + case NM_CVT_S_D: + gen_farith(ctx, OPC_CVT_S_D, -1, rs, rt, 0); + break; + case NM_CVT_S_W: + gen_farith(ctx, OPC_CVT_S_W, -1, rs, rt, 0); + break; + case NM_CVT_S_L: + gen_farith(ctx, OPC_CVT_S_L, -1, rs, rt, 0); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + } + break; + } + break; + case NM_POOL32F_5: + switch ((ctx->opcode >> 3) & 0x07) { + case NM_CMP_CONDN_S: + gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); + break; + case NM_CMP_CONDN_D: + gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } +} + static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) { uint16_t insn; @@ -16887,6 +17186,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } break; case NM_POOL32F: + gen_pool32f_nanomips_insn(ctx); break; case NM_POOL32S: break; From patchwork Thu Jul 19 12:54:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946320 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WZtd6zqFz9s5c for ; Thu, 19 Jul 2018 23:41:45 +1000 (AEST) Received: from localhost ([::1]:43029 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9Bf-0004gD-9W for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:41:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49079) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8VX-0003Ay-00 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8UT-0005e3-0k for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:58:10 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56925 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8UR-0005cK-Lf for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:57:04 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 32D721A415B; Thu, 19 Jul 2018 14:57:02 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 1567F1A1D42; Thu, 19 Jul 2018 14:57:02 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:45 +0200 Message-Id: <1532004912-13899-14-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:09 -0400 Subject: [Qemu-devel] [PATCH v3 13/40] target/mips: Add emulation of misc nanoMIPS instructions (pool32a0) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Add emulation of nanoMIPS instructions that are situated in pool32a0. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic --- target/mips/translate.c | 190 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 190 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 2c7f62e..81c2950 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16588,6 +16588,186 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx) } } +static void gen_pool32a0_nanomips_insn(DisasContext *ctx) +{ + int rt = (ctx->opcode >> 21) & 0x1f; + int rs = (ctx->opcode >> 16) & 0x1f; + int rd = (ctx->opcode >> 11) & 0x1f; + + switch ((ctx->opcode >> 3) & 0x7f) { + case NM_P_TRAP: + switch ((ctx->opcode >> 10) & 0x1) { + case NM_TEQ: + gen_trap(ctx, OPC_TEQ, rs, rt, -1); + break; + case NM_TNE: + gen_trap(ctx, OPC_TNE, rs, rt, -1); + break; + } + break; + case NM_RDHWR: + gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3)); + break; + case NM_SEB: + gen_bshfl(ctx, OPC_SEB, rs, rt); + break; + case NM_SEH: + gen_bshfl(ctx, OPC_SEH, rs, rt); + break; + case NM_SLLV: + gen_shift(ctx, OPC_SLLV, rd, rt, rs); + break; + case NM_SRLV: + gen_shift(ctx, OPC_SRLV, rd, rt, rs); + break; + case NM_SRAV: + gen_shift(ctx, OPC_SRAV, rd, rt, rs); + break; + case NM_ROTRV: + gen_shift(ctx, OPC_ROTRV, rd, rt, rs); + break; + case NM_ADD: + gen_arith(ctx, OPC_ADD, rd, rs, rt); + break; + case NM_ADDU: + gen_arith(ctx, OPC_ADDU, rd, rs, rt); + break; + case NM_SUB: + gen_arith(ctx, OPC_SUB, rd, rs, rt); + break; + case NM_SUBU: + gen_arith(ctx, OPC_SUBU, rd, rs, rt); + break; + case NM_P_CMOVE: + switch ((ctx->opcode >> 10) & 1) { + case NM_MOVZ: + gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt); + break; + case NM_MOVN: + gen_cond_move(ctx, OPC_MOVN, rd, rs, rt); + break; + } + break; + case NM_AND: + gen_logic(ctx, OPC_AND, rd, rs, rt); + break; + case NM_OR: + gen_logic(ctx, OPC_OR, rd, rs, rt); + break; + case NM_NOR: + gen_logic(ctx, OPC_NOR, rd, rs, rt); + break; + case NM_XOR: + gen_logic(ctx, OPC_XOR, rd, rs, rt); + break; + case NM_SLT: + gen_slt(ctx, OPC_SLT, rd, rs, rt); + break; + case NM_P_SLTU: + if (rd == 0) { + /* P_DVP */ +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + switch ((ctx->opcode >> 10) & 1) { + case NM_DVP: + if (ctx->vp) { + check_cp0_enabled(ctx); + gen_helper_dvp(t0, cpu_env); + gen_store_gpr(t0, rt); + } + break; + case NM_EVP: + if (ctx->vp) { + check_cp0_enabled(ctx); + gen_helper_evp(t0, cpu_env); + gen_store_gpr(t0, rt); + } + break; + } + tcg_temp_free(t0); +#endif + } else { + gen_slt(ctx, OPC_SLTU, rd, rs, rt); + } + break; + case NM_SOV: + { + TCGv t0 = tcg_temp_local_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + TCGLabel *l1 = gen_new_label(); + + gen_load_gpr(t1, rs); + gen_load_gpr(t2, rt); + tcg_gen_add_tl(t0, t1, t2); + tcg_gen_ext32s_tl(t0, t0); + tcg_gen_xor_tl(t1, t1, t2); + tcg_gen_xor_tl(t2, t0, t2); + tcg_gen_andc_tl(t1, t2, t1); + + tcg_gen_movi_tl(t0, 0); + tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); + /* operands of same sign, result different sign */ + + tcg_gen_movi_tl(t0, 1); + gen_set_label(l1); + gen_store_gpr(t0, rd); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + } + break; + case NM_MUL: + gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt); + break; + case NM_MUH: + gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt); + break; + case NM_MULU: + gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt); + break; + case NM_MUHU: + gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt); + break; + case NM_DIV: + gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt); + break; + case NM_MOD: + gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt); + break; + case NM_DIVU: + gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt); + break; + case NM_MODU: + gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt); + break; +#ifndef CONFIG_USER_ONLY + case NM_MFC0: + check_cp0_enabled(ctx); + if (rt == 0) { + /* Treat as NOP. */ + break; + } + gen_mfc0(ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7); + break; + case NM_MTC0: + check_cp0_enabled(ctx); + { + TCGv t0 = tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7); + tcg_temp_free(t0); + } + break; +#endif + default: + generate_exception_end(ctx, EXCP_RI); + break; + } +} + static void gen_pool32f_nanomips_insn(DisasContext *ctx) { int rt, rs, rd; @@ -16952,6 +17132,16 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } break; case NM_POOL32A: + switch (ctx->opcode & 0x07) { + case NM_POOL32A0: + gen_pool32a0_nanomips_insn(ctx); + break; + case NM_POOL32A7: + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } break; case NM_P_GP_W: switch (ctx->opcode & 0x03) { From patchwork Thu Jul 19 12:54:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946379 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbPM0Bv1z9s7c for ; Fri, 20 Jul 2018 00:04:53 +1000 (AEST) Received: from localhost ([::1]:43215 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9Y2-0007jR-8V for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:04:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53673) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Xm-0003nZ-D8 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:03:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Ua-0005jb-DV for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:00:30 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57050 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8UZ-0005iQ-OJ for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:57:12 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 504EB1A4574; Thu, 19 Jul 2018 14:57:10 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 328391A4570; Thu, 19 Jul 2018 14:57:10 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:46 +0200 Message-Id: <1532004912-13899-15-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 14/40] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Add emulation of misc nanoMIPS instructions situated in pool32axf. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic Reviewed-by: Richard Henderson --- target/mips/translate.c | 94 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 81c2950..af7825a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16768,6 +16768,93 @@ static void gen_pool32a0_nanomips_insn(DisasContext *ctx) } } +static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) +{ + int rt = (ctx->opcode >> 21) & 0x1f; + int rs = (ctx->opcode >> 16) & 0x1f; + + switch ((ctx->opcode >> 6) & 0x07) { + case NM_POOL32AXF_4: + case NM_POOL32AXF_5: + switch ((ctx->opcode >> 9) & 0x7f) { + case NM_CLO: + gen_cl(ctx, OPC_CLO, rt, rs); + break; + case NM_CLZ: + gen_cl(ctx, OPC_CLZ, rt, rs); + break; +#ifndef CONFIG_USER_ONLY + case NM_TLBP: + gen_cp0(env, ctx, OPC_TLBP, 0, 0); + break; + case NM_TLBR: + gen_cp0(env, ctx, OPC_TLBR, 0, 0); + break; + case NM_TLBWI: + gen_cp0(env, ctx, OPC_TLBWI, 0, 0); + break; + case NM_TLBWR: + gen_cp0(env, ctx, OPC_TLBWR, 0, 0); + break; + case NM_TLBINV: + gen_cp0(env, ctx, OPC_TLBINV, 0, 0); + break; + case NM_TLBINVF: + gen_cp0(env, ctx, OPC_TLBINVF, 0, 0); + break; + case NM_DI: + check_cp0_enabled(ctx); + { + TCGv t0 = tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_helper_di(t0, cpu_env); + gen_store_gpr(t0, rt); + /* Stop translation as we may have switched the execution mode */ + ctx->base.is_jmp = DISAS_STOP; + tcg_temp_free(t0); + } + break; + case NM_EI: + check_cp0_enabled(ctx); + { + TCGv t0 = tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_helper_ei(t0, cpu_env); + gen_store_gpr(t0, rt); + /* Stop translation as we may have switched the execution mode */ + ctx->base.is_jmp = DISAS_STOP; + tcg_temp_free(t0); + } + break; + case NM_RDPGPR: + gen_load_srsgpr(rs, rt); + break; + case NM_WRPGPR: + gen_store_srsgpr(rs, rt); + break; + case NM_WAIT: + gen_cp0(env, ctx, OPC_WAIT, 0, 0); + break; + case NM_DERET: + gen_cp0(env, ctx, OPC_DERET, 0, 0); + break; + case NM_ERETX: + gen_cp0(env, ctx, OPC_ERET, 0, 0); + break; +#endif + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } +} + static void gen_pool32f_nanomips_insn(DisasContext *ctx) { int rt, rs, rd; @@ -17137,6 +17224,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_pool32a0_nanomips_insn(ctx); break; case NM_POOL32A7: + { + switch ((ctx->opcode >> 3) & 0x07) { + case NM_POOL32AXF: + gen_pool32axf_nanomips_insn(env, ctx); + break; + } + } break; default: generate_exception_end(ctx, EXCP_RI); From patchwork Thu Jul 19 12:54:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946326 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WZxv5pLPz9s9F for ; Thu, 19 Jul 2018 23:44:35 +1000 (AEST) Received: from localhost ([::1]:43043 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9EP-00070W-D8 for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:44:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49362) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Vl-0003CK-V0 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Uh-0005ns-V2 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:58:25 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57104 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8Uh-0005mi-9p for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:57:19 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 7F2E61A415B; Thu, 19 Jul 2018 14:57:17 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 619371A4156; Thu, 19 Jul 2018 14:57:17 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:47 +0200 Message-Id: <1532004912-13899-16-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 15/40] target/mips: Add emulation of misc nanoMIPS instructions (pool p_lsx) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Add emulation of nanoMIPS instructions situated in pool p_lsx, and emulation of LSA instruction as well. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic --- target/mips/translate.c | 139 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 138 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index af7825a..f3753bb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16855,6 +16855,132 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) } } + +static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt) +{ + TCGv t0, t1; + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + tcg_gen_movi_tl(t1, 0); + if (rs == 0) { + tcg_gen_movi_tl(t0, 0); + } else { + gen_load_gpr(t0, rs); + } + if (rt == 0) { + tcg_gen_movi_tl(t1, 0); + } else { + gen_load_gpr(t1, rt); + } + if (((ctx->opcode >> 6) & 1) == 1) { + /* PP.LSXS instructions require shifting */ + switch ((ctx->opcode >> 7) & 0xf) { + case NM_LHXS: + case NM_SHXS: + case NM_LHUXS: + tcg_gen_shli_tl(t0, t0, 1); + break; + case NM_LWXS: + case NM_SWXS: + case NM_LWC1XS: + case NM_SWC1XS: + tcg_gen_shli_tl(t0, t0, 2); + break; + case NM_LDC1XS: + case NM_SDC1XS: + tcg_gen_shli_tl(t0, t0, 3); + break; + } + } + gen_op_addr_add(ctx, t0, t0, t1); + + switch ((ctx->opcode >> 7) & 0xf) { + case NM_LBX: + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, + MO_SB); + gen_store_gpr(t0, rd); + break; + case NM_LHX: + /*case NM_LHXS:*/ + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, + MO_TESW); + gen_store_gpr(t0, rd); + break; + case NM_LWX: + /*case NM_LWXS:*/ + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, + MO_TESL); + gen_store_gpr(t0, rd); + break; + case NM_LBUX: + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, + MO_UB); + gen_store_gpr(t0, rd); + break; + case NM_LHUX: + /*case NM_LHUXS:*/ + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, + MO_TEUW); + gen_store_gpr(t0, rd); + break; + case NM_SBX: + gen_load_gpr(t1, rd); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, + MO_8); + break; + case NM_SHX: + /*case NM_SHXS:*/ + gen_load_gpr(t1, rd); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, + MO_TEUW); + break; + case NM_SWX: + /*case NM_SWXS:*/ + gen_load_gpr(t1, rd); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, + MO_TEUL); + break; + case NM_LWC1X: + /*case NM_LWC1XS:*/ + case NM_LDC1X: + /*case NM_LDC1XS:*/ + case NM_SWC1X: + /*case NM_SWC1XS:*/ + case NM_SDC1X: + /*case NM_SDC1XS:*/ + if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { + check_cp1_enabled(ctx); + switch ((ctx->opcode >> 7) & 0xf) { + case NM_LWC1X: + /*case NM_LWC1XS:*/ + gen_flt_ldst(ctx, OPC_LWC1, rd, t0); + break; + case NM_LDC1X: + /*case NM_LDC1XS:*/ + gen_flt_ldst(ctx, OPC_LDC1, rd, t0); + break; + case NM_SWC1X: + /*case NM_SWC1XS:*/ + gen_flt_ldst(ctx, OPC_SWC1, rd, t0); + break; + case NM_SDC1X: + /*case NM_SDC1XS:*/ + gen_flt_ldst(ctx, OPC_SDC1, rd, t0); + break; + } + } else { + generate_exception_err(ctx, EXCP_CpU, 1); + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + static void gen_pool32f_nanomips_insn(DisasContext *ctx) { int rt, rs, rd; @@ -17157,7 +17283,7 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx) static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) { uint16_t insn; - int rt, rs; + int rt, rs, rd; uint32_t op; insn = cpu_lduw_code(env, ctx->base.pc_next + 2); @@ -17165,6 +17291,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) rt = (ctx->opcode >> 21) & 0x1f; rs = (ctx->opcode >> 16) & 0x1f; + rd = (ctx->opcode >> 11) & 0x1f; op = (ctx->opcode >> 26) & 0x3f; switch (op) { @@ -17226,6 +17353,16 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) case NM_POOL32A7: { switch ((ctx->opcode >> 3) & 0x07) { + case NM_P_LSX: + gen_p_lsx(ctx, rd, rs, rt); + break; + case NM_LSA: + /* In nanoMIPS, the shift field directly encodes the shift + * amount, meaning that the supported shift values are in + * the range 0 to 3 (instead of 1 to 4 in MIPSR6). */ + gen_lsa(ctx, OPC_LSA, rd, rs, rt, + extract32(ctx->opcode, 9, 2) - 1); + break; case NM_POOL32AXF: gen_pool32axf_nanomips_insn(env, ctx); break; From patchwork Thu Jul 19 12:54:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946393 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Wbbp4KvMz9s5c for ; Fri, 20 Jul 2018 00:13:58 +1000 (AEST) Received: from localhost ([::1]:43275 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9gq-0007dX-29 for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:13:56 -0400 Received: from eggs.gnu.org ([208.118.235.92]:52240) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8ax-000542-60 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:05:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8V3-00065H-7Q for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:58:47 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57262 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8V2-000649-DH for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:57:40 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id EF27B1A22AF; Thu, 19 Jul 2018 14:57:38 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id D0D701A1D42; Thu, 19 Jul 2018 14:57:38 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:48 +0200 Message-Id: <1532004912-13899-17-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 16/40] target/mips: Implement emulation of nanoMIPS ROTX instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Matthew Fortune Added a helper for ROTX based on the pseudocode from the architecture spec. This instraction was not present in previous MIPS instruction sets. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic Reviewed-by: Richard Henderson --- target/mips/helper.h | 2 ++ target/mips/op_helper.c | 94 +++++++++++++++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 15 ++++++++ 3 files changed, 111 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index 5f49234..b2a780a 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -40,6 +40,8 @@ DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl) #endif +DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32) + #ifndef CONFIG_USER_ONLY /* CP0 helpers */ DEF_HELPER_1(mfc0_mvpcontrol, tl, env) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 0b2663b..b3eef9f 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -249,6 +249,100 @@ target_ulong helper_bitswap(target_ulong rt) return (int32_t)bitswap(rt); } +target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx, + uint32_t stripe) +{ + int i; + uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff); + uint64_t tmp1 = tmp0; + for (i = 0; i <= 46; i++) { + int s; + if (i & 0x8) { + s = shift; + } else { + s = shiftx; + } + + if (stripe != 0 && !(i & 0x4)) { + s = ~s; + } + if (s & 0x10) { + if (tmp0 & (1LL << (i + 16))) { + tmp1 |= 1LL << i; + } else { + tmp1 &= ~(1LL << i); + } + } + } + + uint64_t tmp2 = tmp1; + for (i = 0; i <= 38; i++) { + int s; + if (i & 0x4) { + s = shift; + } else { + s = shiftx; + } + + if (s & 0x8) { + if (tmp1 & (1LL << (i + 8))) { + tmp2 |= 1LL << i; + } else { + tmp2 &= ~(1LL << i); + } + } + } + + uint64_t tmp3 = tmp2; + for (i = 0; i <= 34; i++) { + int s; + if (i & 0x2) { + s = shift; + } else { + s = shiftx; + } + if (s & 0x4) { + if (tmp2 & (1LL << (i + 4))) { + tmp3 |= 1LL << i; + } else { + tmp3 &= ~(1LL << i); + } + } + } + + uint64_t tmp4 = tmp3; + for (i = 0; i <= 32; i++) { + int s; + if (i & 0x1) { + s = shift; + } else { + s = shiftx; + } + if (s & 0x2) { + if (tmp3 & (1LL << (i + 2))) { + tmp4 |= 1LL << i; + } else { + tmp4 &= ~(1LL << i); + } + } + } + + uint64_t tmp5 = tmp4; + for (i = 0; i <= 31; i++) { + int s; + s = shift; + if (s & 0x1) { + if (tmp4 & (1LL << (i + 1))) { + tmp5 |= 1LL << i; + } else { + tmp5 &= ~(1LL << i); + } + } + } + + return (int64_t)(int32_t)(uint32_t)tmp5; +} + #ifndef CONFIG_USER_ONLY static inline hwaddr do_translate_address(CPUMIPSState *env, diff --git a/target/mips/translate.c b/target/mips/translate.c index f3753bb..3cff488 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -17578,6 +17578,21 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } break; case NM_P_ROTX: + if (rt != 0) { + TCGv t0 = tcg_temp_new(); + TCGv_i32 shift = tcg_const_i32(extract32(ctx->opcode, 0, 5)); + TCGv_i32 shiftx = tcg_const_i32(extract32(ctx->opcode, 7, 4) + << 1); + TCGv_i32 stripe = tcg_const_i32((ctx->opcode >> 6) & 1); + + gen_load_gpr(t0, rs); + gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe); + tcg_temp_free(t0); + + tcg_temp_free_i32(shift); + tcg_temp_free_i32(shiftx); + tcg_temp_free_i32(stripe); + } break; case NM_P_INS: switch (((ctx->opcode >> 10) & 2) | ((ctx->opcode >> 5) & 1)) { From patchwork Thu Jul 19 12:54:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946389 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbY20dBBz9s4r for ; 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Thu, 19 Jul 2018 14:57:44 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:49 +0200 Message-Id: <1532004912-13899-18-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 17/40] target/mips: Implement emulation of nanoMIPS EXTW instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: James Hogan Implement emulation of nanoMIPS EXTW instruction, which is similar to the MIPS r6 ALIGN instruction, except that it counts the other way and in bits instead of bytes. We therefore generalise gen_align() into gen_align_bits() (which counts in bits instead of bytes and optimises when bits = size of the word), and implement gen_align() and a new gen_ext() based on that. Since we need to know the word size to check for when the number of bits == the word size, the opc argument is replaced with a wordsz argument (either 32 or 64). Signed-off-by: James Hogan Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Richard Henderson --- target/mips/translate.c | 53 +++++++++++++++++++++++++++++++++---------------- 1 file changed, 36 insertions(+), 17 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 3cff488..29d1f19 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4723,8 +4723,8 @@ static void gen_lsa(DisasContext *ctx, int opc, int rd, int rs, int rt, return; } -static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt, - int bp) +static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs, + int rt, int bits) { TCGv t0; if (rd == 0) { @@ -4732,35 +4732,40 @@ static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt, return; } t0 = tcg_temp_new(); - gen_load_gpr(t0, rt); - if (bp == 0) { - switch (opc) { - case OPC_ALIGN: + if (bits == 0 || bits == wordsz) { + if (bits == 0) { + gen_load_gpr(t0, rt); + } else { + gen_load_gpr(t0, rs); + } + switch (wordsz) { + case 32: tcg_gen_ext32s_tl(cpu_gpr[rd], t0); break; #if defined(TARGET_MIPS64) - case OPC_DALIGN: + case 64: tcg_gen_mov_tl(cpu_gpr[rd], t0); break; #endif } } else { TCGv t1 = tcg_temp_new(); + gen_load_gpr(t0, rt); gen_load_gpr(t1, rs); - switch (opc) { - case OPC_ALIGN: + switch (wordsz) { + case 32: { TCGv_i64 t2 = tcg_temp_new_i64(); tcg_gen_concat_tl_i64(t2, t1, t0); - tcg_gen_shri_i64(t2, t2, 8 * (4 - bp)); + tcg_gen_shri_i64(t2, t2, 32 - bits); gen_move_low32(cpu_gpr[rd], t2); tcg_temp_free_i64(t2); } break; #if defined(TARGET_MIPS64) - case OPC_DALIGN: - tcg_gen_shli_tl(t0, t0, 8 * bp); - tcg_gen_shri_tl(t1, t1, 8 * (8 - bp)); + case 64: + tcg_gen_shli_tl(t0, t0, bits); + tcg_gen_shri_tl(t1, t1, 64 - bits); tcg_gen_or_tl(cpu_gpr[rd], t1, t0); break; #endif @@ -4771,6 +4776,18 @@ static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt, tcg_temp_free(t0); } +static void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, + int bp) +{ + gen_align_bits(ctx, wordsz, rd, rs, rt, bp * 8); +} + +static void gen_ext(DisasContext *ctx, int wordsz, int rd, int rs, int rt, + int shift) +{ + gen_align_bits(ctx, wordsz, rd, rs, rt, wordsz - shift); +} + static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt) { TCGv t0; @@ -14233,8 +14250,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) break; case ALIGN: check_insn(ctx, ISA_MIPS32R6); - gen_align(ctx, OPC_ALIGN, rd, rs, rt, - extract32(ctx->opcode, 9, 2)); + gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2)); break; case EXT: gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd); @@ -17363,6 +17379,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_lsa(ctx, OPC_LSA, rd, rs, rt, extract32(ctx->opcode, 9, 2) - 1); break; + case NM_EXTW: + gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5)); + break; case NM_POOL32AXF: gen_pool32axf_nanomips_insn(env, ctx); break; @@ -20258,7 +20277,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) switch (op2) { case OPC_ALIGN: case OPC_ALIGN_END: - gen_align(ctx, OPC_ALIGN, rd, rs, rt, sa & 3); + gen_align(ctx, 32, rd, rs, rt, sa & 3); break; case OPC_BITSWAP: gen_bitswap(ctx, op2, rd, rt); @@ -20284,7 +20303,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) switch (op2) { case OPC_DALIGN: case OPC_DALIGN_END: - gen_align(ctx, OPC_DALIGN, rd, rs, rt, sa & 7); + gen_align(ctx, 64, rd, rs, rt, sa & 7); break; case OPC_DBITSWAP: gen_bitswap(ctx, op2, rd, rt); From patchwork Thu Jul 19 12:54:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946334 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Wb5M6Lmpz9s4r for ; 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Thu, 19 Jul 2018 14:57:50 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:50 +0200 Message-Id: <1532004912-13899-19-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 18/40] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Add emulation of various nanoMIPS load and store instructions. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic --- target/mips/translate.c | 271 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 271 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 29d1f19..5dc6582 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -17668,10 +17668,281 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } break; case NM_P_GP_BH: + { + uint32_t u = extract32(ctx->opcode, 0, 18); + switch ((ctx->opcode >> 18) & 0x7) { + case NM_LBGP: + gen_ld(ctx, OPC_LB, rt, 28, u); + break; + case NM_SBGP: + gen_st(ctx, OPC_SB, rt, 28, u); + break; + case NM_LBUGP: + gen_ld(ctx, OPC_LBU, rt, 28, u); + break; + case NM_ADDIUGP_B: + gen_arith_imm(ctx, OPC_ADDIU, rt, 28, u); + break; + case NM_P_GP_LH: + u &= ~1; + switch (ctx->opcode & 1) { + case NM_LHGP: + gen_ld(ctx, OPC_LH, rt, 28, u); + break; + case NM_LHUGP: + gen_ld(ctx, OPC_LHU, rt, 28, u); + break; + } + break; + case NM_P_GP_SH: + u &= ~1; + switch (ctx->opcode & 1) { + case NM_SHGP: + gen_st(ctx, OPC_SH, rt, 28, u); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_P_GP_CP1: + u &= ~0x3; + switch ((ctx->opcode & 0x3)) { + case NM_LWC1GP: + gen_cop1_ldst(ctx, OPC_LWC1, rt, 28, u); + break; + case NM_LDC1GP: + gen_cop1_ldst(ctx, OPC_LDC1, rt, 28, u); + break; + case NM_SWC1GP: + gen_cop1_ldst(ctx, OPC_SWC1, rt, 28, u); + break; + case NM_SDC1GP: + gen_cop1_ldst(ctx, OPC_SDC1, rt, 28, u); + break; + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_P_LS_U12: + { + uint32_t u = extract32(ctx->opcode, 0, 12); + switch ((ctx->opcode >> 12) & 0x0f) { + case NM_P_PREFU12: + if (rt == 31) { + /* SYNCI */ + /* Break the TB to be able to sync copied instructions + immediately */ + ctx->base.is_jmp = DISAS_STOP; + } else { + /* PREF */ + /* Treat as NOP. */ + } + break; + case NM_LB: + gen_ld(ctx, OPC_LB, rt, rs, u); + break; + case NM_LH: + gen_ld(ctx, OPC_LH, rt, rs, u); + break; + case NM_LW: + gen_ld(ctx, OPC_LW, rt, rs, u); + break; + case NM_LBU: + gen_ld(ctx, OPC_LBU, rt, rs, u); + break; + case NM_LHU: + gen_ld(ctx, OPC_LHU, rt, rs, u); + break; + case NM_SB: + gen_st(ctx, OPC_SB, rt, rs, u); + break; + case NM_SH: + gen_st(ctx, OPC_SH, rt, rs, u); + break; + case NM_SW: + gen_st(ctx, OPC_SW, rt, rs, u); + break; + case NM_LWC1: + gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, u); + break; + case NM_LDC1: + gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, u); + break; + case NM_SWC1: + gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, u); + break; + case NM_SDC1: + gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, u); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_P_LS_S9: + { + int32_t s = (sextract32(ctx->opcode, 15, 1) << 8) | + extract32(ctx->opcode, 0, 8); + switch ((ctx->opcode >> 8) & 0x07) { + case NM_P_LS_S0: + switch ((ctx->opcode >> 11) & 0x0f) { + case NM_LBS9: + gen_ld(ctx, OPC_LB, rt, rs, s); + break; + case NM_LHS9: + gen_ld(ctx, OPC_LH, rt, rs, s); + break; + case NM_LWS9: + gen_ld(ctx, OPC_LW, rt, rs, s); + break; + case NM_LBUS9: + gen_ld(ctx, OPC_LBU, rt, rs, s); + break; + case NM_LHUS9: + gen_ld(ctx, OPC_LHU, rt, rs, s); + break; + case NM_SBS9: + gen_st(ctx, OPC_SB, rt, rs, s); + break; + case NM_SHS9: + gen_st(ctx, OPC_SH, rt, rs, s); + break; + case NM_SWS9: + gen_st(ctx, OPC_SW, rt, rs, s); + break; + case NM_LWC1S9: + gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, s); + break; + case NM_LDC1S9: + gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, s); + break; + case NM_SWC1S9: + gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, s); + break; + case NM_SDC1S9: + gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, s); + break; + case NM_P_PREFS9: + if (rt == 31) { + /* SYNCI */ + /* Break the TB to be able to sync copied instructions + immediately */ + ctx->base.is_jmp = DISAS_STOP; + } else { + /* PREF */ + /* Treat as NOP. */ + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_P_LS_S1: + switch ((ctx->opcode >> 11) & 0x0f) { + case NM_UALH: + case NM_UASH: + { + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + gen_base_offset_addr(ctx, t0, rs, s); + + switch ((ctx->opcode >> 11) & 0x0f) { + case NM_UALH: + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW | + MO_UNALN); + gen_store_gpr(t0, rt); + break; + case NM_UASH: + gen_load_gpr(t1, rt); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW | + MO_UNALN); + break; + } + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + case NM_P_LL: + switch (ctx->opcode & 0x03) { + case NM_LL: + gen_ld(ctx, OPC_LL, rt, rs, s); + break; + case NM_LLWP: + break; + } + break; + case NM_P_SC: + switch (ctx->opcode & 0x03) { + case NM_SC: + gen_st_cond(ctx, OPC_SC, rt, rs, s); + break; + case NM_SCWP: + break; + } + break; + case NM_CACHE: + check_cp0_enabled(ctx); + if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { + gen_cache_operation(ctx, rt, rs, s); + } + break; + } + break; + case NM_P_LS_WM: + case NM_P_LS_UAWM: + { + int32_t offset = sextract32(ctx->opcode, 15, 1) << 8 | + extract32(ctx->opcode, 0, 8); + int count = extract32(ctx->opcode, 12, 3); + int counter = 0; + TCGv va = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGMemOp memop = ((ctx->opcode >> 8) & 0x07) == NM_P_LS_UAWM ? + MO_UNALN : 0; + + count = (count == 0) ? 8 : count; + while (counter != count) { + int this_rt = ((rt + counter) & 0x1f) | (rt & 0x10); + int32_t this_offset = offset + (counter << 2); + + gen_base_offset_addr(ctx, va, rs, this_offset); + + switch (extract32(ctx->opcode, 11, 1)) { + case NM_LWM: + tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx, + memop | MO_TESL); + gen_store_gpr(t1, this_rt); + if ((this_rt == rs) && + (counter != (count - 1))) { + /* UNPREDICTABLE */ + } + break; + case NM_SWM: + this_rt = (rt == 0) ? 0 : this_rt; + gen_load_gpr(t1, this_rt); + tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx, + memop | MO_TEUL); + break; + } + counter++; + } + tcg_temp_free(va); + tcg_temp_free(t1); + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_MOVE_BALC: break; From patchwork Thu Jul 19 12:54:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946346 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Wb9168Ydz9s55 for ; Thu, 19 Jul 2018 23:54:13 +1000 (AEST) Received: from localhost ([::1]:43093 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9Nj-0006o7-Ec for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:54:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50804) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8WP-0003Jn-Fe for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:00:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8VL-0006IW-FJ for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:05 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57353 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8VK-0006HR-So for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:57:59 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 6D6921A22B2; Thu, 19 Jul 2018 14:57:57 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 4FB6B1A1D42; Thu, 19 Jul 2018 14:57:57 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:51 +0200 Message-Id: <1532004912-13899-20-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 19/40] target/mips: Add emulation of nanoMIPS branch instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Add emulation of various flavors of nanoMIPS branch instructions. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic --- target/mips/translate.c | 277 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 277 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 5dc6582..50b31de 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16871,6 +16871,168 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) } } +/* Immediate Value Compact Branches */ +static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, + int rt, int32_t imm, int32_t offset) +{ + int bcond_compute = 0; + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { +#ifdef MIPS_DEBUG_DISAS + LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx + "\n", ctx->base.pc_next); +#endif + generate_exception_end(ctx, EXCP_RI); + goto out; + } + + gen_load_gpr(t0, rt); + tcg_gen_movi_tl(t1, imm); + ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); + + /* Load needed operands and calculate btarget */ + switch (opc) { + case NM_BEQIC: + if (rt == 0 && imm == 0) { + /* Unconditional branch */ + } else if (rt == 0 && imm != 0) { + /* Treat as NOP */ + goto out; + } else { + bcond_compute = 1; + } + break; + case NM_BBEQZC: + case NM_BBNEZC: + if (imm >= 32 && !(ctx->hflags & MIPS_HFLAG_64)) { + generate_exception_end(ctx, EXCP_RI); + goto out; + } else if (rt == 0 && opc == NM_BBEQZC) { + /* Unconditional branch */ + } else if (rt == 0 && opc == NM_BBNEZC) { + /* Treat as NOP */ + goto out; + } else { + tcg_gen_shri_tl(t0, t0, imm); + tcg_gen_andi_tl(t0, t0, 1); + tcg_gen_movi_tl(t1, 0); + bcond_compute = 1; + } + break; + case NM_BNEIC: + if (rt == 0 && imm == 0) { + /* Treat as NOP */ + goto out; + } else if (rt == 0 && imm != 0) { + /* Unconditional branch */ + } else { + bcond_compute = 1; + } + break; + case NM_BGEIC: + if (rt == 0 && imm == 0) { + /* Unconditional branch */ + } else { + bcond_compute = 1; + } + break; + case NM_BLTIC: + bcond_compute = 1; + break; + case NM_BGEIUC: + if (rt == 0 && imm == 0) { + /* Unconditional branch */ + } else { + bcond_compute = 1; + } + break; + case NM_BLTIUC: + bcond_compute = 1; + break; + default: + MIPS_INVAL("Immediate Value Compact branch"); + generate_exception_end(ctx, EXCP_RI); + goto out; + } + + if (bcond_compute == 0) { + /* Uncoditional compact branch */ + ctx->hflags |= MIPS_HFLAG_B; + /* Generating branch here as compact branches don't have delay slot */ + gen_branch(ctx, 4); + } else { + /* Conditional compact branch */ + TCGLabel *fs = gen_new_label(); + save_cpu_state(ctx, 0); + + switch (opc) { + case NM_BEQIC: + tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs); + break; + case NM_BBEQZC: + tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs); + break; + case NM_BNEIC: + tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs); + break; + case NM_BBNEZC: + tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs); + break; + case NM_BGEIC: + tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs); + break; + case NM_BLTIC: + tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs); + break; + case NM_BGEIUC: + tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs); + break; + case NM_BLTIUC: + tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs); + break; + } + + /* Generating branch here as compact branches don't have delay slot */ + gen_goto_tb(ctx, 1, ctx->btarget); + gen_set_label(fs); + + ctx->hflags |= MIPS_HFLAG_FBNSLOT; + } + +out: + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +/* P.BALRSC type nanoMIPS R6 branches: BALRSC and BRSC */ +static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs, + int rt) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + /* load rs */ + gen_load_gpr(t0, rs); + + /* link */ + if (rt != 0) { + tcg_gen_movi_tl(cpu_gpr[rt], ctx->base.pc_next + 4); + } + + /* calculate btarget */ + tcg_gen_shli_tl(t0, t0, 1); + tcg_gen_movi_tl(t1, ctx->base.pc_next + 4); + gen_op_addr_add(ctx, btarget, t1, t0); + + ctx->hflags |= MIPS_HFLAG_BR; + /* Generating branch here as compact branches don't have delay slot */ + gen_branch(ctx, 4); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt) { @@ -17945,16 +18107,131 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } break; case NM_MOVE_BALC: + { + TCGv t0 = tcg_temp_new(); + int32_t s = sextract32(ctx->opcode, 0, 1) << 21 | + extract32(ctx->opcode, 1, 20) << 1; + rd = ((ctx->opcode >> 24) & 1) == 0 ? 4 : 5; + rt = decode_gpr_gpr4_zero(extract32(ctx->opcode, 25, 1) << 3 | + extract32(ctx->opcode, 21, 3)); + gen_load_gpr(t0, rt); + tcg_gen_mov_tl(cpu_gpr[rd], t0); + gen_compute_branch(ctx, OPC_BGEZAL, 4, 0, 0, s, 0); + tcg_temp_free(t0); + } break; case NM_P_BAL: + { + int32_t s = sextract32(ctx->opcode, 0, 1) << 25 | + extract32(ctx->opcode, 1, 24) << 1; + + if (((ctx->opcode >> 25) & 1) == 0) { + /* BC */ + gen_compute_branch(ctx, OPC_BEQ, 4, 0, 0, s, 0); + } else { + /* BALC */ + gen_compute_branch(ctx, OPC_BGEZAL, 4, 0, 0, s, 0); + } + } break; case NM_P_J: + switch ((ctx->opcode >> 12) & 0x0f) { + case NM_JALRC: + case NM_JALRC_HB: + gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0); + break; + case NM_P_BALRSC: + gen_compute_nanomips_pbalrsc_branch(ctx, rs, rt); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } break; case NM_P_BR1: + { + int32_t s = sextract32(ctx->opcode, 0, 1) << 14 | + extract32(ctx->opcode, 1, 13) << 1; + switch ((ctx->opcode >> 14) & 0x03) { + case NM_BEQC: + gen_compute_branch(ctx, OPC_BEQ, 4, rs, rt, s, 0); + break; + case NM_P_BR3A: + { + int32_t s = sextract32(ctx->opcode, 0, 1) << 14 | + extract32(ctx->opcode, 1, 13) << 1; + check_cp1_enabled(ctx); + switch ((ctx->opcode >> 16) & 0x1f) { + case NM_BC1EQZC: + gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rt, s, 0); + break; + case NM_BC1NEZC: + gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rt, s, 0); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } + break; + case NM_BGEC: + if (rs == rt) { + gen_compute_compact_branch(ctx, OPC_BC, rs, rt, s); + } else { + gen_compute_compact_branch(ctx, OPC_BGEC, rs, rt, s); + } + break; + case NM_BGEUC: + if (rs == rt || rt == 0) { + gen_compute_compact_branch(ctx, OPC_BC, 0, 0, s); + } else if (rs == 0) { + gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0, s); + } else { + gen_compute_compact_branch(ctx, OPC_BGEUC, rs, rt, s); + } + break; + } + } break; case NM_P_BR2: + { + int32_t s = sextract32(ctx->opcode, 0, 1) << 14 | + extract32(ctx->opcode, 1, 13) << 1; + switch ((ctx->opcode >> 14) & 0x03) { + case NM_BNEC: + gen_compute_branch(ctx, OPC_BNE, 4, rs, rt, s, 0); + break; + case NM_BLTC: + if (rs != 0 && rt != 0 && rs == rt) { + /* NOP */ + ctx->hflags |= MIPS_HFLAG_FBNSLOT; + } else { + gen_compute_compact_branch(ctx, OPC_BLTC, rs, rt, s); + } + break; + case NM_BLTUC: + if (rs == 0 || rs == rt) { + /* NOP */ + ctx->hflags |= MIPS_HFLAG_FBNSLOT; + } else { + gen_compute_compact_branch(ctx, OPC_BLTUC, rs, rt, s); + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_P_BRI: + { + int32_t s = sextract32(ctx->opcode, 0, 1) << 11 | + extract32(ctx->opcode, 1, 10) << 1; + uint32_t u = extract32(ctx->opcode, 11, 7); + + gen_compute_imm_branch(ctx, extract32(ctx->opcode, 18, 3), + rt, u, s); + } break; default: generate_exception_end(ctx, EXCP_RI); From patchwork Thu Jul 19 12:54:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946374 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbLQ6SyHz9s5c for ; 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Thu, 19 Jul 2018 14:58:02 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:52 +0200 Message-Id: <1532004912-13899-21-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 20/40] target/mips: Implement MT ASE support for nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Stefan Markovic Add emulation of MT ASE instructions for nanoMIPS. Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Richard Henderson --- target/mips/translate.c | 85 +++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 83 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 50b31de..c8a9ba0 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16604,7 +16604,7 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx) } } -static void gen_pool32a0_nanomips_insn(DisasContext *ctx) +static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) { int rt = (ctx->opcode >> 21) & 0x1f; int rs = (ctx->opcode >> 16) & 0x1f; @@ -16777,6 +16777,87 @@ static void gen_pool32a0_nanomips_insn(DisasContext *ctx) tcg_temp_free(t0); } break; + case NM_D_E_MT_VPE: + { + uint8_t sc = (ctx->opcode >> 10) & 1; + TCGv t0 = tcg_temp_new(); + + switch (sc) { + case 0: + if (rs == 1) { + /* DMT */ + check_insn(ctx, ASE_MT); + gen_helper_dmt(t0); + gen_store_gpr(t0, rt); + } else if (rs == 0) { + /* DVPE */ + check_insn(ctx, ASE_MT); + gen_helper_dvpe(t0, cpu_env); + gen_store_gpr(t0, rt); + } else { + generate_exception_end(ctx, EXCP_RI); + } + break; + case 1: + if (rs == 1) { + /* EMT */ + check_insn(ctx, ASE_MT); + gen_helper_emt(t0); + gen_store_gpr(t0, rt); + } else if (rs == 0) { + /* EVPE */ + check_insn(ctx, ASE_MT); + gen_helper_evpe(t0, cpu_env); + gen_store_gpr(t0, rt); + } else { + generate_exception_end(ctx, EXCP_RI); + } + break; + } + + tcg_temp_free(t0); + } + break; + case NM_FORK: + check_insn(ctx, ASE_MT); + { + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_load_gpr(t1, rs); + gen_helper_fork(t0, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + case NM_MFTR: + case NM_MFHTR: + check_insn(ctx, ASE_MT); + if (rd == 0) { + /* Treat as NOP. */ + return; + } + gen_mftr(env, ctx, rs, rt, (ctx->opcode >> 10) & 1, + (ctx->opcode >> 11) & 0x1f, (ctx->opcode >> 3) & 1); + break; + case NM_MTTR: + case NM_MTHTR: + check_insn(ctx, ASE_MT); + gen_mttr(env, ctx, rs, rt, (ctx->opcode >> 10) & 1, + (ctx->opcode >> 11) & 0x1f, (ctx->opcode >> 3) & 1); + break; + case NM_YIELD: + check_insn(ctx, ASE_MT); + { + TCGv t0 = tcg_temp_new(); + + gen_load_gpr(t0, rs); + gen_helper_yield(t0, cpu_env, t0); + gen_store_gpr(t0, rt); + tcg_temp_free(t0); + } + break; #endif default: generate_exception_end(ctx, EXCP_RI); @@ -17526,7 +17607,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) case NM_POOL32A: switch (ctx->opcode & 0x07) { case NM_POOL32A0: - gen_pool32a0_nanomips_insn(ctx); + gen_pool32a0_nanomips_insn(env, ctx); break; case NM_POOL32A7: { From patchwork Thu Jul 19 12:54:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946368 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbHl1t4tz9s4r for ; Fri, 20 Jul 2018 00:00:03 +1000 (AEST) Received: from localhost ([::1]:43124 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9TM-0003YA-Ss for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:00:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54492) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8YI-0004FZ-IB for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:02:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8VX-0006Qd-J3 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:01:02 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57460 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8VW-0006Ow-7o for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:58:11 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id BEEF51A44FF; Thu, 19 Jul 2018 14:58:08 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 97FE41A1D42; Thu, 19 Jul 2018 14:58:08 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:53 +0200 Message-Id: <1532004912-13899-22-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 21/40] target/mips: Implement DSP ASE support for nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Stefan Markovic Add emulation of DSP ASE instructions for nanoMIPS. Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 2072 ++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 1681 insertions(+), 391 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index c8a9ba0..d7454a6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -14064,6 +14064,527 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs) } } + +static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc, + int rd, int rs, int rt) +{ + int ret = rd; + + TCGv t1; + TCGv v1_t; + TCGv v2_t; + + t1 = tcg_temp_new(); + v1_t = tcg_temp_new(); + v2_t = tcg_temp_new(); + + gen_load_gpr(v1_t, rs); + gen_load_gpr(v2_t, rt); + + switch (opc) { + case OPC_CMP_EQ_PH: + check_dsp(ctx); + gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env); + break; + case OPC_CMP_LT_PH: + check_dsp(ctx); + gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env); + break; + case OPC_CMP_LE_PH: + check_dsp(ctx); + gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env); + break; + case OPC_CMPU_EQ_QB: + check_dsp(ctx); + gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env); + break; + case OPC_CMPU_LT_QB: + check_dsp(ctx); + gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env); + break; + case OPC_CMPU_LE_QB: + check_dsp(ctx); + gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env); + break; + case OPC_CMPGU_EQ_QB: + check_dsp(ctx); + gen_helper_cmpgu_eq_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_CMPGU_LT_QB: + check_dsp(ctx); + gen_helper_cmpgu_lt_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_CMPGU_LE_QB: + check_dsp(ctx); + gen_helper_cmpgu_le_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_CMPGDU_EQ_QB: + check_dspr2(ctx); + gen_helper_cmpgu_eq_qb(t1, v1_t, v2_t); + tcg_gen_mov_tl(cpu_gpr[ret], t1); + tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); + tcg_gen_shli_tl(t1, t1, 24); + tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); + break; + case OPC_CMPGDU_LT_QB: + check_dspr2(ctx); + gen_helper_cmpgu_lt_qb(t1, v1_t, v2_t); + tcg_gen_mov_tl(cpu_gpr[ret], t1); + tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); + tcg_gen_shli_tl(t1, t1, 24); + tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); + break; + case OPC_CMPGDU_LE_QB: + check_dspr2(ctx); + gen_helper_cmpgu_le_qb(t1, v1_t, v2_t); + tcg_gen_mov_tl(cpu_gpr[ret], t1); + tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); + tcg_gen_shli_tl(t1, t1, 24); + tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); + break; + case OPC_PACKRL_PH: + check_dsp(ctx); + gen_helper_packrl_ph(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_PICK_QB: + check_dsp(ctx); + gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_PICK_PH: + check_dsp(ctx); + gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDQ_S_W: + check_dsp(ctx); + gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SUBQ_S_W: + check_dsp(ctx); + gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDSC: + check_dsp(ctx); + gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDWC: + check_dsp(ctx); + gen_helper_addwc(cpu_gpr[rd], v1_t, v2_t, cpu_env); + break; + case OPC_ADDQ_S_PH: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* ADDQ_PH */ + check_dsp(ctx); + gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case 1: + /* ADDQ_S_PH */ + check_dsp(ctx); + gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + } + break; + case OPC_ADDQH_R_PH: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* ADDQH_PH */ + gen_helper_addqh_ph(cpu_gpr[ret], v1_t, v2_t); + break; + case 1: + /* ADDQH_R_PH */ + gen_helper_addqh_r_ph(cpu_gpr[ret], v1_t, v2_t); + break; + } + break; + case OPC_ADDQH_R_W: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* ADDQH_W */ + gen_helper_addqh_w(cpu_gpr[ret], v1_t, v2_t); + break; + case 1: + /* ADDQH_R_W */ + gen_helper_addqh_r_w(cpu_gpr[ret], v1_t, v2_t); + break; + } + break; + case OPC_ADDU_S_QB: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* ADDU_QB */ + check_dsp(ctx); + gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case 1: + /* ADDU_S_QB */ + check_dsp(ctx); + gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + } + break; + case OPC_ADDU_S_PH: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* ADDU_PH */ + check_dspr2(ctx); + gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case 1: + /* ADDU_S_PH */ + check_dspr2(ctx); + gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + } + break; + case OPC_ADDUH_R_QB: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* ADDUH_QB */ + gen_helper_adduh_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case 1: + /* ADDUH_R_QB */ + gen_helper_adduh_r_qb(cpu_gpr[ret], v1_t, v2_t); + break; + } + break; + case OPC_SHRAV_R_PH: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* SHRAV_PH */ + check_dsp(ctx); + gen_helper_shra_ph(cpu_gpr[ret], v1_t, v2_t); + break; + case 1: + /* SHRAV_R_PH */ + check_dsp(ctx); + gen_helper_shra_r_ph(cpu_gpr[ret], v1_t, v2_t); + break; + } + break; + case OPC_SHRAV_R_QB: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* SHRAV_QB */ + check_dspr2(ctx); + gen_helper_shra_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case 1: + /* SHRAV_R_QB */ + check_dspr2(ctx); + gen_helper_shra_r_qb(cpu_gpr[ret], v1_t, v2_t); + break; + } + break; + case OPC_SUBQ_S_PH: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* SUBQ_PH */ + check_dsp(ctx); + gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case 1: + /* SUBQ_S_PH */ + check_dsp(ctx); + gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + } + break; + case OPC_SUBQH_R_PH: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* SUBQH_PH */ + gen_helper_subqh_ph(cpu_gpr[ret], v1_t, v2_t); + break; + case 1: + /* SUBQH_R_PH */ + gen_helper_subqh_r_ph(cpu_gpr[ret], v1_t, v2_t); + break; + } + break; + case OPC_SUBQH_R_W: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* SUBQH_W */ + gen_helper_subqh_w(cpu_gpr[ret], v1_t, v2_t); + break; + case 1: + /* SUBQH_R_W */ + gen_helper_subqh_r_w(cpu_gpr[ret], v1_t, v2_t); + break; + } + break; + case OPC_SUBU_S_QB: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* SUBU_QB */ + check_dsp(ctx); + gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case 1: + /* SUBU_S_QB */ + check_dsp(ctx); + gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + } + break; + case OPC_SUBU_S_PH: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* SUBU_PH */ + check_dspr2(ctx); + gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case 1: + /* SUBU_S_PH */ + check_dspr2(ctx); + gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + } + break; + case OPC_SUBUH_R_QB: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* SUBUH_QB */ + gen_helper_subuh_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case 1: + /* SUBUH_R_QB */ + gen_helper_subuh_r_qb(cpu_gpr[ret], v1_t, v2_t); + break; + } + break; + case OPC_SHLLV_S_PH: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* SHLLV_PH */ + check_dsp(ctx); + gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case 1: + /* SHLLV_S_PH */ + check_dsp(ctx); + gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + } + break; + case OPC_PRECR_SRA_R_PH_W: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* PRECR_SRA_PH_W */ + check_dspr2(ctx); + { + TCGv_i32 sa_t = tcg_const_i32(rd); + gen_helper_precr_sra_ph_w(cpu_gpr[rt], sa_t, v1_t, + cpu_gpr[rt]); + tcg_temp_free_i32(sa_t); + } + break; + case 1: + /* PRECR_SRA_R_PH_W */ + check_dspr2(ctx); + { + TCGv_i32 sa_t = tcg_const_i32(rd); + gen_helper_precr_sra_r_ph_w(cpu_gpr[rt], sa_t, v1_t, + cpu_gpr[rt]); + tcg_temp_free_i32(sa_t); + } + break; + } + break; + case OPC_MULEU_S_PH_QBL: + check_dsp(ctx); + gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULEU_S_PH_QBR: + check_dsp(ctx); + gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULQ_RS_PH: + check_dsp(ctx); + gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULQ_S_PH: + check_dspr2(ctx); + gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULQ_RS_W: + gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULQ_S_W: + gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_APPEND: + { + TCGv t0; + + t0 = tcg_temp_new(); + gen_load_gpr(t0, rs); + + if (rd != 0) { + tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], rd, 32 - rd); + } + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } + break; + case OPC_MODSUB: + check_dsp(ctx); + gen_helper_modsub(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SHRAV_R_W: + check_dsp(ctx); + gen_helper_shra_r_w(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SHRLV_PH: + check_dspr2(ctx); + gen_helper_shrl_ph(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SHRLV_QB: + check_dsp(ctx); + gen_helper_shrl_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SHLLV_QB: + check_dsp(ctx); + gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SHLLV_S_W: + check_dsp(ctx); + gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SHILO: + { + TCGv t0; + TCGv t1; + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + + int16_t imm = (ctx->opcode >> 16) & 0x3F; + + tcg_gen_movi_tl(t0, rd >> 3); + tcg_gen_movi_tl(t1, imm); + + gen_helper_shilo(t0, t1, cpu_env); + } + break; + case OPC_MULEQ_S_W_PHL: + check_dsp(ctx); + gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULEQ_S_W_PHR: + check_dsp(ctx); + gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MUL_S_PH: + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* MUL_PH */ + gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case 1: + /* MUL_S_PH */ + gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + } + break; + case OPC_PRECR_QB_PH: + check_dspr2(ctx); + gen_helper_precr_qb_ph(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_PRECRQ_QB_PH: + check_dsp(ctx); + gen_helper_precrq_qb_ph(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_PRECRQ_PH_W: + check_dsp(ctx); + gen_helper_precrq_ph_w(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_PRECRQ_RS_PH_W: + check_dsp(ctx); + gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_PRECRQU_S_QB_PH: + check_dsp(ctx); + gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SHRA_R_W: + { + TCGv t0; + t0 = tcg_temp_new(); + tcg_gen_movi_tl(t0, rd); + + check_dsp(ctx); + gen_helper_shra_r_w(cpu_gpr[rt], t0, v1_t); + break; + } + case OPC_SHRA_R_PH: + { + TCGv t0; + t0 = tcg_temp_new(); + tcg_gen_movi_tl(t0, rd >> 1); + + switch ((ctx->opcode >> 10) & 0x1) { + case 0: + /* SHRA_PH */ + check_dsp(ctx); + gen_helper_shra_ph(cpu_gpr[rt], t0, v1_t); + break; + case 1: + /* SHRA_R_PH */ + check_dsp(ctx); + gen_helper_shra_r_ph(cpu_gpr[rt], t0, v1_t); + break; + } + } + break; + case OPC_SHLL_S_PH: + { + TCGv t0; + t0 = tcg_temp_new(); + tcg_gen_movi_tl(t0, rd >> 1); + + switch ((ctx->opcode >> 10) & 0x3) { + case 0: + /* SHLL_PH */ + check_dsp(ctx); + gen_helper_shll_ph(cpu_gpr[rt], t0, v1_t, cpu_env); + break; + case 2: + /* SHLL_S_PH */ + check_dsp(ctx); + gen_helper_shll_s_ph(cpu_gpr[rt], t0, v1_t, cpu_env); + break; + } + } + break; + case OPC_SHLL_S_W: + { + TCGv t0; + t0 = tcg_temp_new(); + tcg_gen_movi_tl(t0, rd); + + check_dsp(ctx); + gen_helper_shll_s_w(cpu_gpr[rt], t0, v1_t, cpu_env); + break; + } + break; + case OPC_REPL_PH: + check_dsp(ctx); + { + int16_t imm; + imm = (ctx->opcode >> 11) & 0x03FF; + imm = (int16_t)(imm << 6) >> 6; + tcg_gen_movi_tl(cpu_gpr[rt], \ + (target_long)((int32_t)imm << 16 | \ + (uint16_t)imm)); + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } +} + + static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) { int32_t offset; @@ -16370,508 +16891,1253 @@ enum { NM_LWC1X = 0x0a, NM_LDC1X = 0x0e, - NM_LWUX = 0x07, - NM_SWC1X = 0x0b, - NM_SDC1X = 0x0f, + NM_LWUX = 0x07, + NM_SWC1X = 0x0b, + NM_SDC1X = 0x0f, + + NM_LHXS = 0x04, + NM_LWXS = 0x08, + NM_LDXS = 0x0c, + + NM_SHXS = 0x05, + NM_SWXS = 0x09, + NM_SDXS = 0x0d, + + NM_LHUXS = 0x06, + NM_LWC1XS = 0x0a, + NM_LDC1XS = 0x0e, + + NM_LWUXS = 0x07, + NM_SWC1XS = 0x0b, + NM_SDC1XS = 0x0f, +}; + +/* ERETx instruction pool */ +enum { + NM_ERET = 0x00, + NM_ERETNC = 0x01, +}; + +/* POOL32FxF_{0, 1} insturction pool */ +enum { + NM_CFC1 = 0x40, + NM_CTC1 = 0x60, + NM_MFC1 = 0x80, + NM_MTC1 = 0xa0, + NM_MFHC1 = 0xc0, + NM_MTHC1 = 0xe0, + + NM_CVT_S_PL = 0x84, + NM_CVT_S_PU = 0xa4, + + NM_CVT_L_S = 0x004, + NM_CVT_L_D = 0x104, + NM_CVT_W_S = 0x024, + NM_CVT_W_D = 0x124, + + NM_RSQRT_S = 0x008, + NM_RSQRT_D = 0x108, + + NM_SQRT_S = 0x028, + NM_SQRT_D = 0x128, + + NM_RECIP_S = 0x048, + NM_RECIP_D = 0x148, + + NM_FLOOR_L_S = 0x00c, + NM_FLOOR_L_D = 0x10c, + + NM_FLOOR_W_S = 0x02c, + NM_FLOOR_W_D = 0x12c, + + NM_CEIL_L_S = 0x04c, + NM_CEIL_L_D = 0x14c, + NM_CEIL_W_S = 0x06c, + NM_CEIL_W_D = 0x16c, + NM_TRUNC_L_S = 0x08c, + NM_TRUNC_L_D = 0x18c, + NM_TRUNC_W_S = 0x0ac, + NM_TRUNC_W_D = 0x1ac, + NM_ROUND_L_S = 0x0cc, + NM_ROUND_L_D = 0x1cc, + NM_ROUND_W_S = 0x0ec, + NM_ROUND_W_D = 0x1ec, + + NM_MOV_S = 0x01, + NM_MOV_D = 0x81, + NM_ABS_S = 0x0d, + NM_ABS_D = 0x8d, + NM_NEG_S = 0x2d, + NM_NEG_D = 0xad, + NM_CVT_D_S = 0x04d, + NM_CVT_D_W = 0x0cd, + NM_CVT_D_L = 0x14d, + NM_CVT_S_D = 0x06d, + NM_CVT_S_W = 0x0ed, + NM_CVT_S_L = 0x16d, +}; + +/* P.LL instruction pool */ +enum { + NM_LL = 0x00, + NM_LLWP = 0x01, +}; + +/* P.SC instruction pool */ +enum { + NM_SC = 0x00, + NM_SCWP = 0x01, +}; + +/* P.DVP instruction pool */ +enum { + NM_DVP = 0x00, + NM_EVP = 0x01, +}; + + +/* + * + * nanoMIPS decoding engine + * + */ + +static int decode_gpr_gpr3(int r) +{ + static const int map[] = { 16, 17, 18, 19, 4, 5, 6, 7 }; + + return map[r & 0x7]; +} + +/* Used for 16-bit store instructions. */ +static int decode_gpr_gpr3_src_store(int r) +{ + static const int map[] = { 0, 17, 18, 19, 4, 5, 6, 7 }; + + return map[r & 0x7]; +} + +static int decode_gpr_gpr4(int r) +{ + static const int map[] = { 8, 9, 10, 11, 4, 5, 6, 7, + 16, 17, 18, 19, 20, 21, 22, 23 }; + + return map[r & 0xf]; +} + +/* Used for 16-bit store instructions. */ +static int decode_gpr_gpr4_zero(int r) +{ + static const int map[] = { 8, 9, 10, 0, 4, 5, 6, 7, + 16, 17, 18, 19, 20, 21, 22, 23 }; + + return map[r & 0xf]; +} + + +/* extraction utilities */ + +#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7) +#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7) +#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op) +#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7) +#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f) +#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f) + + +static void gen_adjust_sp(DisasContext *ctx, int u) +{ + TCGv tsp = tcg_temp_new(); + gen_base_offset_addr(ctx, tsp, 29, u); + gen_store_gpr(tsp, 29); + tcg_temp_free(tsp); +} + +static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count, + uint8_t gp, uint16_t u) +{ + int counter = 0; + TCGv va = tcg_temp_new(); + TCGv t0 = tcg_temp_new(); + + while (counter != count) { + bool use_gp = gp && (counter == count - 1); + int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f); + int this_offset = -((counter + 1) << 2); + gen_base_offset_addr(ctx, va, 29, this_offset); + gen_load_gpr(t0, this_rt); + tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx, + MO_TEUL | ctx->default_tcg_memop_mask); + counter++; + } - NM_LHXS = 0x04, - NM_LWXS = 0x08, - NM_LDXS = 0x0c, + /* adjust stack pointer */ + gen_adjust_sp(ctx, -u); - NM_SHXS = 0x05, - NM_SWXS = 0x09, - NM_SDXS = 0x0d, + tcg_temp_free(t0); + tcg_temp_free(va); +} - NM_LHUXS = 0x06, - NM_LWC1XS = 0x0a, - NM_LDC1XS = 0x0e, +static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count, + uint8_t gp, uint16_t u) +{ + int counter = 0; + TCGv va = tcg_temp_new(); + TCGv t0 = tcg_temp_new(); - NM_LWUXS = 0x07, - NM_SWC1XS = 0x0b, - NM_SDC1XS = 0x0f, -}; + while (counter != count) { + bool use_gp = gp && (counter == count - 1); + int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f); + int this_offset = u - ((counter + 1) << 2); + gen_base_offset_addr(ctx, va, 29, this_offset); + tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TESL | + ctx->default_tcg_memop_mask); + tcg_gen_ext32s_tl(t0, t0); + gen_store_gpr(t0, this_rt); + counter++; + } -/* ERETx instruction pool */ -enum { - NM_ERET = 0x00, - NM_ERETNC = 0x01, -}; + /* adjust stack pointer */ + gen_adjust_sp(ctx, u); -/* POOL32FxF_{0, 1} insturction pool */ -enum { - NM_CFC1 = 0x40, - NM_CTC1 = 0x60, - NM_MFC1 = 0x80, - NM_MTC1 = 0xa0, - NM_MFHC1 = 0xc0, - NM_MTHC1 = 0xe0, + tcg_temp_free(t0); + tcg_temp_free(va); +} - NM_CVT_S_PL = 0x84, - NM_CVT_S_PU = 0xa4, +static void gen_pool16c_nanomips_insn(DisasContext *ctx) +{ + int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode)); + int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode)); - NM_CVT_L_S = 0x004, - NM_CVT_L_D = 0x104, - NM_CVT_W_S = 0x024, - NM_CVT_W_D = 0x124, + switch ((ctx->opcode >> 2) & 0x3) { + case NM_NOT16: + gen_logic(ctx, OPC_NOR, rt, rs, 0); + break; + case NM_AND16: + gen_logic(ctx, OPC_AND, rt, rt, rs); + break; + case NM_XOR16: + gen_logic(ctx, OPC_XOR, rt, rt, rs); + break; + case NM_OR16: + gen_logic(ctx, OPC_OR, rt, rt, rs); + break; + } +} - NM_RSQRT_S = 0x008, - NM_RSQRT_D = 0x108, +static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) +{ + int rt = (ctx->opcode >> 21) & 0x1f; + int rs = (ctx->opcode >> 16) & 0x1f; + int rd = (ctx->opcode >> 11) & 0x1f; - NM_SQRT_S = 0x028, - NM_SQRT_D = 0x128, + switch ((ctx->opcode >> 3) & 0x7f) { + case NM_P_TRAP: + switch ((ctx->opcode >> 10) & 0x1) { + case NM_TEQ: + gen_trap(ctx, OPC_TEQ, rs, rt, -1); + break; + case NM_TNE: + gen_trap(ctx, OPC_TNE, rs, rt, -1); + break; + } + break; + case NM_RDHWR: + gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3)); + break; + case NM_SEB: + gen_bshfl(ctx, OPC_SEB, rs, rt); + break; + case NM_SEH: + gen_bshfl(ctx, OPC_SEH, rs, rt); + break; + case NM_SLLV: + gen_shift(ctx, OPC_SLLV, rd, rt, rs); + break; + case NM_SRLV: + gen_shift(ctx, OPC_SRLV, rd, rt, rs); + break; + case NM_SRAV: + gen_shift(ctx, OPC_SRAV, rd, rt, rs); + break; + case NM_ROTRV: + gen_shift(ctx, OPC_ROTRV, rd, rt, rs); + break; + case NM_ADD: + gen_arith(ctx, OPC_ADD, rd, rs, rt); + break; + case NM_ADDU: + gen_arith(ctx, OPC_ADDU, rd, rs, rt); + break; + case NM_SUB: + gen_arith(ctx, OPC_SUB, rd, rs, rt); + break; + case NM_SUBU: + gen_arith(ctx, OPC_SUBU, rd, rs, rt); + break; + case NM_P_CMOVE: + switch ((ctx->opcode >> 10) & 1) { + case NM_MOVZ: + gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt); + break; + case NM_MOVN: + gen_cond_move(ctx, OPC_MOVN, rd, rs, rt); + break; + } + break; + case NM_AND: + gen_logic(ctx, OPC_AND, rd, rs, rt); + break; + case NM_OR: + gen_logic(ctx, OPC_OR, rd, rs, rt); + break; + case NM_NOR: + gen_logic(ctx, OPC_NOR, rd, rs, rt); + break; + case NM_XOR: + gen_logic(ctx, OPC_XOR, rd, rs, rt); + break; + case NM_SLT: + gen_slt(ctx, OPC_SLT, rd, rs, rt); + break; + case NM_P_SLTU: + if (rd == 0) { + /* P_DVP */ +#ifndef CONFIG_USER_ONLY + TCGv t0 = tcg_temp_new(); + switch ((ctx->opcode >> 10) & 1) { + case NM_DVP: + if (ctx->vp) { + check_cp0_enabled(ctx); + gen_helper_dvp(t0, cpu_env); + gen_store_gpr(t0, rt); + } + break; + case NM_EVP: + if (ctx->vp) { + check_cp0_enabled(ctx); + gen_helper_evp(t0, cpu_env); + gen_store_gpr(t0, rt); + } + break; + } + tcg_temp_free(t0); +#endif + } else { + gen_slt(ctx, OPC_SLTU, rd, rs, rt); + } + break; + case NM_SOV: + { + TCGv t0 = tcg_temp_local_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + TCGLabel *l1 = gen_new_label(); - NM_RECIP_S = 0x048, - NM_RECIP_D = 0x148, + gen_load_gpr(t1, rs); + gen_load_gpr(t2, rt); + tcg_gen_add_tl(t0, t1, t2); + tcg_gen_ext32s_tl(t0, t0); + tcg_gen_xor_tl(t1, t1, t2); + tcg_gen_xor_tl(t2, t0, t2); + tcg_gen_andc_tl(t1, t2, t1); - NM_FLOOR_L_S = 0x00c, - NM_FLOOR_L_D = 0x10c, + tcg_gen_movi_tl(t0, 0); + tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); + /* operands of same sign, result different sign */ - NM_FLOOR_W_S = 0x02c, - NM_FLOOR_W_D = 0x12c, + tcg_gen_movi_tl(t0, 1); + gen_set_label(l1); + gen_store_gpr(t0, rd); - NM_CEIL_L_S = 0x04c, - NM_CEIL_L_D = 0x14c, - NM_CEIL_W_S = 0x06c, - NM_CEIL_W_D = 0x16c, - NM_TRUNC_L_S = 0x08c, - NM_TRUNC_L_D = 0x18c, - NM_TRUNC_W_S = 0x0ac, - NM_TRUNC_W_D = 0x1ac, - NM_ROUND_L_S = 0x0cc, - NM_ROUND_L_D = 0x1cc, - NM_ROUND_W_S = 0x0ec, - NM_ROUND_W_D = 0x1ec, + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + } + break; + case NM_MUL: + gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt); + break; + case NM_MUH: + gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt); + break; + case NM_MULU: + gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt); + break; + case NM_MUHU: + gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt); + break; + case NM_DIV: + gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt); + break; + case NM_MOD: + gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt); + break; + case NM_DIVU: + gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt); + break; + case NM_MODU: + gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt); + break; +#ifndef CONFIG_USER_ONLY + case NM_MFC0: + check_cp0_enabled(ctx); + if (rt == 0) { + /* Treat as NOP. */ + break; + } + gen_mfc0(ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7); + break; + case NM_MTC0: + check_cp0_enabled(ctx); + { + TCGv t0 = tcg_temp_new(); - NM_MOV_S = 0x01, - NM_MOV_D = 0x81, - NM_ABS_S = 0x0d, - NM_ABS_D = 0x8d, - NM_NEG_S = 0x2d, - NM_NEG_D = 0xad, - NM_CVT_D_S = 0x04d, - NM_CVT_D_W = 0x0cd, - NM_CVT_D_L = 0x14d, - NM_CVT_S_D = 0x06d, - NM_CVT_S_W = 0x0ed, - NM_CVT_S_L = 0x16d, -}; + gen_load_gpr(t0, rt); + gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7); + tcg_temp_free(t0); + } + break; + case NM_D_E_MT_VPE: + { + uint8_t sc = (ctx->opcode >> 10) & 1; + TCGv t0 = tcg_temp_new(); -/* P.LL instruction pool */ -enum { - NM_LL = 0x00, - NM_LLWP = 0x01, -}; + switch (sc) { + case 0: + if (rs == 1) { + /* DMT */ + check_insn(ctx, ASE_MT); + gen_helper_dmt(t0); + gen_store_gpr(t0, rt); + } else if (rs == 0) { + /* DVPE */ + check_insn(ctx, ASE_MT); + gen_helper_dvpe(t0, cpu_env); + gen_store_gpr(t0, rt); + } else { + generate_exception_end(ctx, EXCP_RI); + } + break; + case 1: + if (rs == 1) { + /* EMT */ + check_insn(ctx, ASE_MT); + gen_helper_emt(t0); + gen_store_gpr(t0, rt); + } else if (rs == 0) { + /* EVPE */ + check_insn(ctx, ASE_MT); + gen_helper_evpe(t0, cpu_env); + gen_store_gpr(t0, rt); + } else { + generate_exception_end(ctx, EXCP_RI); + } + break; + } -/* P.SC instruction pool */ -enum { - NM_SC = 0x00, - NM_SCWP = 0x01, -}; + tcg_temp_free(t0); + } + break; + case NM_FORK: + check_insn(ctx, ASE_MT); + { + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); -/* P.DVP instruction pool */ -enum { - NM_DVP = 0x00, - NM_EVP = 0x01, -}; + gen_load_gpr(t0, rt); + gen_load_gpr(t1, rs); + gen_helper_fork(t0, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + case NM_MFTR: + case NM_MFHTR: + check_insn(ctx, ASE_MT); + if (rd == 0) { + /* Treat as NOP. */ + return; + } + gen_mftr(env, ctx, rs, rt, (ctx->opcode >> 10) & 1, + (ctx->opcode >> 11) & 0x1f, (ctx->opcode >> 3) & 1); + break; + case NM_MTTR: + case NM_MTHTR: + check_insn(ctx, ASE_MT); + gen_mttr(env, ctx, rs, rt, (ctx->opcode >> 10) & 1, + (ctx->opcode >> 11) & 0x1f, (ctx->opcode >> 3) & 1); + break; + case NM_YIELD: + check_insn(ctx, ASE_MT); + { + TCGv t0 = tcg_temp_new(); + gen_load_gpr(t0, rs); + gen_helper_yield(t0, cpu_env, t0); + gen_store_gpr(t0, rt); + tcg_temp_free(t0); + } + break; +#endif + default: + generate_exception_end(ctx, EXCP_RI); + break; + } +} -/* - * - * nanoMIPS decoding engine - * - */ -static int decode_gpr_gpr3(int r) +static void gen_pool32axf_1_5_nanomips_insn(DisasContext *ctx, uint32_t opc, + int ret, int v1, int v2) { - static const int map[] = { 16, 17, 18, 19, 4, 5, 6, 7 }; + TCGv_i32 t0; + TCGv v0_t; + TCGv v1_t; - return map[r & 0x7]; -} + t0 = tcg_temp_new_i32(); -/* Used for 16-bit store instructions. */ -static int decode_gpr_gpr3_src_store(int r) -{ - static const int map[] = { 0, 17, 18, 19, 4, 5, 6, 7 }; + v0_t = tcg_temp_new(); + v1_t = tcg_temp_new(); - return map[r & 0x7]; -} + tcg_gen_movi_i32(t0, v2 >> 3); -static int decode_gpr_gpr4(int r) -{ - static const int map[] = { 8, 9, 10, 11, 4, 5, 6, 7, - 16, 17, 18, 19, 20, 21, 22, 23 }; + gen_load_gpr(v0_t, ret); + gen_load_gpr(v1_t, v1); - return map[r & 0xf]; -} + switch (opc) { + case NM_MAQ_S_W_PHR: + check_dsp(ctx); + gen_helper_maq_s_w_phr(t0, v1_t, v0_t, cpu_env); + break; + case NM_MAQ_S_W_PHL: + check_dsp(ctx); + gen_helper_maq_s_w_phl(t0, v1_t, v0_t, cpu_env); + break; + case NM_MAQ_SA_W_PHR: + check_dsp(ctx); + gen_helper_maq_sa_w_phr(t0, v1_t, v0_t, cpu_env); + break; + case NM_MAQ_SA_W_PHL: + check_dsp(ctx); + gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, cpu_env); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } -/* Used for 16-bit store instructions. */ -static int decode_gpr_gpr4_zero(int r) -{ - static const int map[] = { 8, 9, 10, 0, 4, 5, 6, 7, - 16, 17, 18, 19, 20, 21, 22, 23 }; + tcg_temp_free_i32(t0); - return map[r & 0xf]; + tcg_temp_free(v0_t); + tcg_temp_free(v1_t); } -/* extraction utilities */ +static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc, + int ret, int v1, int v2) +{ + int16_t imm; -#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7) -#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7) -#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op) -#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7) -#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f) -#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f) + TCGv t0; + TCGv t1; + TCGv v0_t; + TCGv v1_t; + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); -static void gen_adjust_sp(DisasContext *ctx, int u) -{ - TCGv tsp = tcg_temp_new(); - gen_base_offset_addr(ctx, tsp, 29, u); - gen_store_gpr(tsp, 29); - tcg_temp_free(tsp); -} + v0_t = tcg_temp_new(); + v1_t = tcg_temp_new(); -static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count, - uint8_t gp, uint16_t u) -{ - int counter = 0; - TCGv va = tcg_temp_new(); - TCGv t0 = tcg_temp_new(); + gen_load_gpr(v0_t, ret); + gen_load_gpr(v1_t, v1); - while (counter != count) { - bool use_gp = gp && (counter == count - 1); - int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f); - int this_offset = -((counter + 1) << 2); - gen_base_offset_addr(ctx, va, 29, this_offset); - gen_load_gpr(t0, this_rt); - tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx, - (MO_TEUL | ctx->default_tcg_memop_mask)); - counter++; + switch (opc) { + case NM_POOL32AXF_1_0: + switch ((ctx->opcode >> 12) & 0x03) { + case NM_MFHI: + gen_HILO(ctx, OPC_MFHI, v2 >> 3, ret); + break; + case NM_MFLO: + gen_HILO(ctx, OPC_MFLO, v2 >> 3, ret); + break; + case NM_MTHI: + gen_HILO(ctx, OPC_MTHI, v2 >> 3, v1); + break; + case NM_MTLO: + gen_HILO(ctx, OPC_MTLO, v2 >> 3, v1); + break; + } + break; + case NM_POOL32AXF_1_1: + switch ((ctx->opcode >> 12) & 0x03) { + case NM_MTHLIP: + tcg_gen_movi_tl(t0, v2); + gen_helper_mthlip(t0, v1_t, cpu_env); + break; + case NM_SHILOV: + tcg_gen_movi_tl(t0, v2 >> 3); + gen_helper_shilo(t0, v1_t, cpu_env); + break; + } + break; + case NM_POOL32AXF_1_3: + imm = (ctx->opcode >> 14) & 0x07F; + switch ((ctx->opcode >> 12) & 0x03) { + case NM_RDDSP: + tcg_gen_movi_tl(t0, imm); + gen_helper_rddsp(cpu_gpr[ret], t0, cpu_env); + break; + case NM_WRDSP: + tcg_gen_movi_tl(t0, imm); + gen_helper_wrdsp(v0_t, t0, cpu_env); + break; + case NM_EXTP: + tcg_gen_movi_tl(t0, v2 >> 3); + tcg_gen_movi_tl(t1, v1); + gen_helper_extp(cpu_gpr[ret], t0, t1, cpu_env); + break; + case NM_EXTPDP: + tcg_gen_movi_tl(t0, v2 >> 3); + tcg_gen_movi_tl(t1, v1); + gen_helper_extpdp(cpu_gpr[ret], t0, t1, cpu_env); + break; + } + break; + case NM_POOL32AXF_1_4: + tcg_gen_movi_tl(t0, v2 >> 2); + switch ((ctx->opcode >> 12) & 0x01) { + case NM_SHLL_QB: + check_dsp(ctx); + gen_helper_shll_qb(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + case NM_SHRL_QB: + check_dsp(ctx); + gen_helper_shrl_qb(cpu_gpr[ret], t0, v1_t); + break; + } + break; + case NM_POOL32AXF_1_5: + { + uint32_t opc = (ctx->opcode >> 12) & 0x03; + gen_pool32axf_1_5_nanomips_insn(ctx, opc, ret, v1, v2); + } + break; + case NM_POOL32AXF_1_7: + tcg_gen_movi_tl(t0, v2 >> 3); + tcg_gen_movi_tl(t1, v1); + switch ((ctx->opcode >> 12) & 0x03) { + case NM_EXTR_W: + gen_helper_extr_w(cpu_gpr[ret], t0, t1, cpu_env); + break; + case NM_EXTR_R_W: + gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, cpu_env); + break; + case NM_EXTR_RS_W: + gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, cpu_env); + break; + case NM_EXTR_S_H: + gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, cpu_env); + break; + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; } - /* adjust stack pointer */ - gen_adjust_sp(ctx, -u); - tcg_temp_free(t0); - tcg_temp_free(va); + tcg_temp_free(t1); + + tcg_temp_free(v0_t); + tcg_temp_free(v1_t); } -static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count, - uint8_t gp, uint16_t u) +static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc, + int ret, int v1, int v2) { - int counter = 0; - TCGv va = tcg_temp_new(); - TCGv t0 = tcg_temp_new(); + TCGv_i32 t0; + TCGv v0_t; + TCGv v1_t; - while (counter != count) { - bool use_gp = gp && (counter == count - 1); - int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f); - int this_offset = u - ((counter + 1) << 2); - gen_base_offset_addr(ctx, va, 29, this_offset); - tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TESL | - ctx->default_tcg_memop_mask); - tcg_gen_ext32s_tl(t0, t0); - gen_store_gpr(t0, this_rt); - counter++; - } + t0 = tcg_temp_new_i32(); - /* adjust stack pointer */ - gen_adjust_sp(ctx, u); + v0_t = tcg_temp_new(); + v1_t = tcg_temp_new(); - tcg_temp_free(t0); - tcg_temp_free(va); -} + tcg_gen_movi_i32(t0, v2 >> 3); -static void gen_pool16c_nanomips_insn(DisasContext *ctx) -{ - int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode)); - int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode)); + gen_load_gpr(v0_t, ret); + gen_load_gpr(v1_t, v1); - switch ((ctx->opcode >> 2) & 0x3) { - case NM_NOT16: - gen_logic(ctx, OPC_NOR, rt, rs, 0); + switch (opc) { + case NM_POOL32AXF_2_0_7: + switch ((ctx->opcode >> 9) & 0x07) { + case NM_DPA_W_PH: + check_dspr2(ctx); + gen_helper_dpa_w_ph(t0, v1_t, v0_t, cpu_env); + break; + case NM_DPAQ_S_W_PH: + check_dsp(ctx); + gen_helper_dpaq_s_w_ph(t0, v1_t, v0_t, cpu_env); + break; + case NM_DPS_W_PH: + check_dspr2(ctx); + gen_helper_dps_w_ph(t0, v1_t, v0_t, cpu_env); + break; + case NM_DPSQ_S_W_PH: + check_dsp(ctx); + gen_helper_dpsq_s_w_ph(t0, v1_t, v0_t, cpu_env); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } break; - case NM_AND16: - gen_logic(ctx, OPC_AND, rt, rt, rs); + case NM_POOL32AXF_2_8_15: + switch ((ctx->opcode >> 9) & 0x07) { + case NM_DPAX_W_PH: + check_dspr2(ctx); + gen_helper_dpax_w_ph(t0, v0_t, v1_t, cpu_env); + break; + case NM_DPAQ_SA_L_W: + check_dsp(ctx); + gen_helper_dpaq_sa_l_w(t0, v0_t, v1_t, cpu_env); + break; + case NM_DPSX_W_PH: + check_dspr2(ctx); + gen_helper_dpsx_w_ph(t0, v0_t, v1_t, cpu_env); + break; + case NM_DPSQ_SA_L_W: + check_dsp(ctx); + gen_helper_dpsq_sa_l_w(t0, v0_t, v1_t, cpu_env); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } break; - case NM_XOR16: - gen_logic(ctx, OPC_XOR, rt, rt, rs); + case NM_POOL32AXF_2_16_23: + switch ((ctx->opcode >> 9) & 0x07) { + case NM_DPAU_H_QBL: + check_dsp(ctx); + gen_helper_dpau_h_qbl(t0, v0_t, v1_t, cpu_env); + break; + case NM_DPAQX_S_W_PH: + check_dspr2(ctx); + gen_helper_dpaqx_s_w_ph(t0, v0_t, v1_t, cpu_env); + break; + case NM_DPSU_H_QBL: + check_dsp(ctx); + gen_helper_dpsu_h_qbl(t0, v0_t, v1_t, cpu_env); + break; + case NM_DPSQX_S_W_PH: + check_dspr2(ctx); + gen_helper_dpsqx_s_w_ph(t0, v0_t, v1_t, cpu_env); + break; + case NM_MULSA_W_PH: + check_dspr2(ctx); + gen_helper_mulsa_w_ph(t0, v0_t, v1_t, cpu_env); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } break; - case NM_OR16: - gen_logic(ctx, OPC_OR, rt, rt, rs); + case NM_POOL32AXF_2_24_31: + switch ((ctx->opcode >> 9) & 0x07) { + case NM_DPAU_H_QBR: + check_dsp(ctx); + gen_helper_dpau_h_qbr(t0, v1_t, v0_t, cpu_env); + break; + case NM_DPAQX_SA_W_PH: + check_dspr2(ctx); + gen_helper_dpaqx_sa_w_ph(t0, v1_t, v0_t, cpu_env); + break; + case NM_DPSU_H_QBR: + check_dsp(ctx); + gen_helper_dpsu_h_qbr(t0, v1_t, v0_t, cpu_env); + break; + case NM_DPSQX_SA_W_PH: + check_dspr2(ctx); + gen_helper_dpsqx_sa_w_ph(t0, v1_t, v0_t, cpu_env); + break; + case NM_MULSAQ_S_W_PH: + check_dsp(ctx); + gen_helper_mulsaq_s_w_ph(t0, v1_t, v0_t, cpu_env); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + default: + generate_exception_end(ctx, EXCP_RI); break; } + + tcg_temp_free_i32(t0); + + tcg_temp_free(v0_t); + tcg_temp_free(v1_t); } -static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) +static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, + int ret, int v1, int v2) { - int rt = (ctx->opcode >> 21) & 0x1f; - int rs = (ctx->opcode >> 16) & 0x1f; - int rd = (ctx->opcode >> 11) & 0x1f; + TCGv t0; + TCGv t1; - switch ((ctx->opcode >> 3) & 0x7f) { - case NM_P_TRAP: - switch ((ctx->opcode >> 10) & 0x1) { - case NM_TEQ: - gen_trap(ctx, OPC_TEQ, rs, rt, -1); + TCGv v0_t; + TCGv v1_t; + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + + v0_t = tcg_temp_new(); + v1_t = tcg_temp_new(); + + gen_load_gpr(v0_t, ret); + gen_load_gpr(v1_t, v1); + + switch (opc) { + case NM_POOL32AXF_2_0_7: + switch ((ctx->opcode >> 9) & 0x07) { + case NM_DPA_W_PH: + case NM_DPAQ_S_W_PH: + case NM_DPS_W_PH: + case NM_DPSQ_S_W_PH: + gen_pool32axf_2_multiply(ctx, opc, ret, v1, v2); + break; + case NM_BALIGN: + gen_load_gpr(t0, v1); + v2 &= 3; + if (v2 != 0 && v2 != 2) { + tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 8 * v2); + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_shri_tl(t0, t0, 8 * (4 - v2)); + tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); + } + tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); break; - case NM_TNE: - gen_trap(ctx, OPC_TNE, rs, rt, -1); + case NM_MADD: + { + int acc = (ctx->opcode >> 14) & 3; + + gen_load_gpr(t0, ret); + gen_load_gpr(t1, v1); + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_ext_tl_i64(t2, t0); + tcg_gen_ext_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); + tcg_gen_add_i64(t2, t2, t3); + tcg_temp_free_i64(t3); + gen_move_low32(cpu_LO[acc], t2); + gen_move_high32(cpu_HI[acc], t2); + tcg_temp_free_i64(t2); + } + break; + case NM_MULT: + { + int acc = (ctx->opcode >> 14) & 3; + + gen_load_gpr(t0, v1); + gen_load_gpr(t1, ret); + + TCGv_i32 t2 = tcg_temp_new_i32(); + TCGv_i32 t3 = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t2, t0); + tcg_gen_trunc_tl_i32(t3, t1); + tcg_gen_muls2_i32(t2, t3, t2, t3); + tcg_gen_ext_i32_tl(cpu_LO[acc], t2); + tcg_gen_ext_i32_tl(cpu_HI[acc], t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + } + break; + case NM_EXTRV_W: + gen_load_gpr(v1_t, v1); + tcg_gen_movi_tl(t0, v2 >> 3); + gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, cpu_env); break; } break; - case NM_RDHWR: - gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3)); - break; - case NM_SEB: - gen_bshfl(ctx, OPC_SEB, rs, rt); - break; - case NM_SEH: - gen_bshfl(ctx, OPC_SEH, rs, rt); - break; - case NM_SLLV: - gen_shift(ctx, OPC_SLLV, rd, rt, rs); - break; - case NM_SRLV: - gen_shift(ctx, OPC_SRLV, rd, rt, rs); - break; - case NM_SRAV: - gen_shift(ctx, OPC_SRAV, rd, rt, rs); - break; - case NM_ROTRV: - gen_shift(ctx, OPC_ROTRV, rd, rt, rs); - break; - case NM_ADD: - gen_arith(ctx, OPC_ADD, rd, rs, rt); - break; - case NM_ADDU: - gen_arith(ctx, OPC_ADDU, rd, rs, rt); - break; - case NM_SUB: - gen_arith(ctx, OPC_SUB, rd, rs, rt); - break; - case NM_SUBU: - gen_arith(ctx, OPC_SUBU, rd, rs, rt); - break; - case NM_P_CMOVE: - switch ((ctx->opcode >> 10) & 1) { - case NM_MOVZ: - gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt); + case NM_POOL32AXF_2_8_15: + switch ((ctx->opcode >> 9) & 0x07) { + case NM_DPAX_W_PH: + case NM_DPAQ_SA_L_W: + case NM_DPSX_W_PH: + case NM_DPSQ_SA_L_W: + gen_pool32axf_2_multiply(ctx, opc, ret, v1, v2); break; - case NM_MOVN: - gen_cond_move(ctx, OPC_MOVN, rd, rs, rt); + case NM_MADDU: + { + int acc = (ctx->opcode >> 14) & 3; + + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + gen_load_gpr(t0, v1); + gen_load_gpr(t1, ret); + + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_extu_tl_i64(t2, t0); + tcg_gen_extu_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); + tcg_gen_add_i64(t2, t2, t3); + tcg_temp_free_i64(t3); + gen_move_low32(cpu_LO[acc], t2); + gen_move_high32(cpu_HI[acc], t2); + tcg_temp_free_i64(t2); + } + break; + case NM_MULTU: + { + int acc = (ctx->opcode >> 14) & 3; + + TCGv_i32 t2 = tcg_temp_new_i32(); + TCGv_i32 t3 = tcg_temp_new_i32(); + + gen_load_gpr(t0, v1); + gen_load_gpr(t1, ret); + + tcg_gen_trunc_tl_i32(t2, t0); + tcg_gen_trunc_tl_i32(t3, t1); + tcg_gen_mulu2_i32(t2, t3, t2, t3); + tcg_gen_ext_i32_tl(cpu_LO[acc], t2); + tcg_gen_ext_i32_tl(cpu_HI[acc], t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + } + break; + case NM_EXTRV_R_W: + tcg_gen_movi_tl(t0, v2 >> 3); + gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env); break; } break; - case NM_AND: - gen_logic(ctx, OPC_AND, rd, rs, rt); - break; - case NM_OR: - gen_logic(ctx, OPC_OR, rd, rs, rt); - break; - case NM_NOR: - gen_logic(ctx, OPC_NOR, rd, rs, rt); - break; - case NM_XOR: - gen_logic(ctx, OPC_XOR, rd, rs, rt); - break; - case NM_SLT: - gen_slt(ctx, OPC_SLT, rd, rs, rt); - break; - case NM_P_SLTU: - if (rd == 0) { - /* P_DVP */ -#ifndef CONFIG_USER_ONLY - TCGv t0 = tcg_temp_new(); - switch ((ctx->opcode >> 10) & 1) { - case NM_DVP: - if (ctx->vp) { - check_cp0_enabled(ctx); - gen_helper_dvp(t0, cpu_env); - gen_store_gpr(t0, rt); - } - break; - case NM_EVP: - if (ctx->vp) { - check_cp0_enabled(ctx); - gen_helper_evp(t0, cpu_env); - gen_store_gpr(t0, rt); - } - break; + case NM_POOL32AXF_2_16_23: + switch ((ctx->opcode >> 9) & 0x07) { + case NM_DPAU_H_QBL: + case NM_DPAQX_S_W_PH: + case NM_DPSU_H_QBL: + case NM_DPSQX_S_W_PH: + case NM_MULSA_W_PH: + gen_pool32axf_2_multiply(ctx, opc, ret, v1, v2); + break; + case NM_EXTPV: + tcg_gen_movi_tl(t0, v2 >> 3); + gen_helper_extp(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + case NM_MSUB: + { + int acc = (ctx->opcode >> 14) & 3; + + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + gen_load_gpr(t0, v1); + gen_load_gpr(t1, ret); + + tcg_gen_ext_tl_i64(t2, t0); + tcg_gen_ext_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); + tcg_gen_sub_i64(t2, t3, t2); + tcg_temp_free_i64(t3); + gen_move_low32(cpu_LO[acc], t2); + gen_move_high32(cpu_HI[acc], t2); + tcg_temp_free_i64(t2); + } + break; + case NM_EXTRV_RS_W: + tcg_gen_movi_tl(t0, v2 >> 3); + gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + } + break; + case NM_POOL32AXF_2_24_31: + switch ((ctx->opcode >> 9) & 0x07) { + case NM_DPAU_H_QBR: + case NM_DPAQX_SA_W_PH: + case NM_DPSU_H_QBR: + case NM_DPSQX_SA_W_PH: + case NM_MULSAQ_S_W_PH: + gen_pool32axf_2_multiply(ctx, opc, ret, v1, v2); + break; + case NM_EXTPDPV: + tcg_gen_movi_tl(t0, v2 >> 3); + gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + case NM_MSUBU: + { + int acc = (ctx->opcode >> 14) & 3; + + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + gen_load_gpr(t0, v1); + gen_load_gpr(t1, ret); + + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_extu_tl_i64(t2, t0); + tcg_gen_extu_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); + tcg_gen_sub_i64(t2, t3, t2); + tcg_temp_free_i64(t3); + gen_move_low32(cpu_LO[acc], t2); + gen_move_high32(cpu_HI[acc], t2); + tcg_temp_free_i64(t2); } - tcg_temp_free(t0); -#endif - } else { - gen_slt(ctx, OPC_SLTU, rd, rs, rt); + break; + case NM_EXTRV_S_H: + tcg_gen_movi_tl(t0, v2 >> 3); + gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env); + break; } break; - case NM_SOV: - { - TCGv t0 = tcg_temp_local_new(); - TCGv t1 = tcg_temp_new(); - TCGv t2 = tcg_temp_new(); - TCGLabel *l1 = gen_new_label(); + default: + generate_exception_end(ctx, EXCP_RI); + break; + } - gen_load_gpr(t1, rs); - gen_load_gpr(t2, rt); - tcg_gen_add_tl(t0, t1, t2); - tcg_gen_ext32s_tl(t0, t0); - tcg_gen_xor_tl(t1, t1, t2); - tcg_gen_xor_tl(t2, t0, t2); - tcg_gen_andc_tl(t1, t2, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); - tcg_gen_movi_tl(t0, 0); - tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - /* operands of same sign, result different sign */ + tcg_temp_free(v0_t); + tcg_temp_free(v1_t); +} - tcg_gen_movi_tl(t0, 1); - gen_set_label(l1); - gen_store_gpr(t0, rd); +static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc, + int ret, int v1, int v2) +{ + TCGv t0; + TCGv v0_t; + TCGv v1_t; - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - } + t0 = tcg_temp_new(); + + v0_t = tcg_temp_new(); + v1_t = tcg_temp_new(); + + gen_load_gpr(v0_t, ret); + gen_load_gpr(v1_t, v1); + + switch (opc) { + case NM_ABSQ_S_QB: + check_dspr2(ctx); + gen_helper_absq_s_qb(cpu_gpr[ret], v0_t, cpu_env); break; - case NM_MUL: - gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt); + case NM_ABSQ_S_PH: + check_dsp(ctx); + gen_helper_absq_s_ph(cpu_gpr[ret], v1_t, cpu_env); break; - case NM_MUH: - gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt); + case NM_ABSQ_S_W: + check_dsp(ctx); + gen_helper_absq_s_w(cpu_gpr[ret], v1_t, cpu_env); break; - case NM_MULU: - gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt); + case NM_PRECEQ_W_PHL: + check_dsp(ctx); + tcg_gen_andi_tl(cpu_gpr[ret], v1_t, 0xFFFF0000); + tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); break; - case NM_MUHU: - gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt); + case NM_PRECEQ_W_PHR: + check_dsp(ctx); + tcg_gen_andi_tl(cpu_gpr[ret], v1_t, 0x0000FFFF); + tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 16); + tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); break; - case NM_DIV: - gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt); + case NM_PRECEQU_PH_QBL: + check_dsp(ctx); + gen_helper_precequ_ph_qbl(cpu_gpr[ret], v1_t); break; - case NM_MOD: - gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt); + case NM_PRECEQU_PH_QBR: + check_dsp(ctx); + gen_helper_precequ_ph_qbr(cpu_gpr[ret], v1_t); break; - case NM_DIVU: - gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt); + case NM_PRECEQU_PH_QBLA: + check_dsp(ctx); + gen_helper_precequ_ph_qbla(cpu_gpr[ret], v1_t); break; - case NM_MODU: - gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt); + case NM_PRECEQU_PH_QBRA: + check_dsp(ctx); + gen_helper_precequ_ph_qbra(cpu_gpr[ret], v1_t); break; -#ifndef CONFIG_USER_ONLY - case NM_MFC0: - check_cp0_enabled(ctx); - if (rt == 0) { - /* Treat as NOP. */ - break; - } - gen_mfc0(ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7); + case NM_PRECEU_PH_QBL: + check_dsp(ctx); + gen_helper_preceu_ph_qbl(cpu_gpr[ret], v1_t); break; - case NM_MTC0: - check_cp0_enabled(ctx); + case NM_PRECEU_PH_QBR: + check_dsp(ctx); + gen_helper_preceu_ph_qbr(cpu_gpr[ret], v1_t); + break; + case NM_PRECEU_PH_QBLA: + check_dsp(ctx); + gen_helper_preceu_ph_qbla(cpu_gpr[ret], v1_t); + break; + case NM_PRECEU_PH_QBRA: + check_dsp(ctx); + gen_helper_preceu_ph_qbra(cpu_gpr[ret], v1_t); + break; + case NM_REPLV_PH: + check_dsp(ctx); + tcg_gen_ext16u_tl(cpu_gpr[ret], v1_t); + tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); + tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); + tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); + break; + case NM_REPLV_QB: + check_dsp(ctx); { - TCGv t0 = tcg_temp_new(); + TCGv val_t; - gen_load_gpr(t0, rt); - gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7); - tcg_temp_free(t0); + val_t = tcg_temp_new(); + gen_load_gpr(val_t, v1); + + tcg_gen_ext8u_tl(cpu_gpr[ret], val_t); + tcg_gen_shli_tl(t0, cpu_gpr[ret], 8); + tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); + tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); + tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); + tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); } break; - case NM_D_E_MT_VPE: + case NM_BITREV: + check_dsp(ctx); + gen_helper_bitrev(cpu_gpr[ret], v1_t); + break; + case NM_INSV: + check_dsp(ctx); { - uint8_t sc = (ctx->opcode >> 10) & 1; - TCGv t0 = tcg_temp_new(); + TCGv t0, t1; - switch (sc) { - case 0: - if (rs == 1) { - /* DMT */ - check_insn(ctx, ASE_MT); - gen_helper_dmt(t0); - gen_store_gpr(t0, rt); - } else if (rs == 0) { - /* DVPE */ - check_insn(ctx, ASE_MT); - gen_helper_dvpe(t0, cpu_env); - gen_store_gpr(t0, rt); - } else { - generate_exception_end(ctx, EXCP_RI); - } - break; - case 1: - if (rs == 1) { - /* EMT */ - check_insn(ctx, ASE_MT); - gen_helper_emt(t0); - gen_store_gpr(t0, rt); - } else if (rs == 0) { - /* EVPE */ - check_insn(ctx, ASE_MT); - gen_helper_evpe(t0, cpu_env); - gen_store_gpr(t0, rt); - } else { - generate_exception_end(ctx, EXCP_RI); - } - break; - } + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); - tcg_temp_free(t0); - } - break; - case NM_FORK: - check_insn(ctx, ASE_MT); - { - TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); + gen_load_gpr(t0, ret); + gen_load_gpr(t1, v1); + + gen_helper_insv(cpu_gpr[ret], cpu_env, t1, t0); - gen_load_gpr(t0, rt); - gen_load_gpr(t1, rs); - gen_helper_fork(t0, t1); tcg_temp_free(t0); tcg_temp_free(t1); } break; - case NM_MFTR: - case NM_MFHTR: - check_insn(ctx, ASE_MT); - if (rd == 0) { - /* Treat as NOP. */ - return; - } - gen_mftr(env, ctx, rs, rt, (ctx->opcode >> 10) & 1, - (ctx->opcode >> 11) & 0x1f, (ctx->opcode >> 3) & 1); + case NM_RADDU_W_QB: + check_dsp(ctx); + gen_helper_raddu_w_qb(cpu_gpr[ret], v1_t); break; - case NM_MTTR: - case NM_MTHTR: - check_insn(ctx, ASE_MT); - gen_mttr(env, ctx, rs, rt, (ctx->opcode >> 10) & 1, - (ctx->opcode >> 11) & 0x1f, (ctx->opcode >> 3) & 1); + case NM_BITSWAP: + gen_bitswap(ctx, OPC_BITSWAP, ret, v1); break; - case NM_YIELD: - check_insn(ctx, ASE_MT); - { - TCGv t0 = tcg_temp_new(); + case NM_CLO: + gen_cl(ctx, OPC_CLO, ret, v1); + break; + case NM_CLZ: + gen_cl(ctx, OPC_CLZ, ret, v1); + break; + case NM_WSBH: + gen_bshfl(ctx, OPC_WSBH, ret, v1); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } - gen_load_gpr(t0, rs); - gen_helper_yield(t0, cpu_env, t0); - gen_store_gpr(t0, rt); - tcg_temp_free(t0); + tcg_temp_free(t0); + + tcg_temp_free(v0_t); + tcg_temp_free(v1_t); +} + +static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc, + int ret, int v1, int v2) +{ + int16_t imm; + + TCGv t0; + TCGv v1_t; + + t0 = tcg_temp_new(); + v1_t = tcg_temp_new(); + + gen_load_gpr(v1_t, v1); + + switch (opc) { + case NM_SHRA_R_QB: + tcg_gen_movi_tl(t0, v2 >> 2); + switch ((ctx->opcode >> 12) & 0x01) { + case 0: + /* NM_SHRA_QB */ + check_dspr2(ctx); + gen_helper_shra_qb(cpu_gpr[ret], t0, v1_t); + break; + case 1: + /* NM_SHRA_R_QB */ + check_dspr2(ctx); + gen_helper_shra_r_qb(cpu_gpr[ret], t0, v1_t); + break; + } + break; + case NM_SHRL_PH: + check_dspr2(ctx); + tcg_gen_movi_tl(t0, v2 >> 1); + gen_helper_shrl_ph(cpu_gpr[ret], t0, v1_t); + break; + case NM_REPL_QB: + { + check_dsp(ctx); + target_long result; + imm = (ctx->opcode >> 13) & 0xFF; + result = (uint32_t)imm << 24 | + (uint32_t)imm << 16 | + (uint32_t)imm << 8 | + (uint32_t)imm; + result = (int32_t)result; + tcg_gen_movi_tl(cpu_gpr[ret], result); } break; -#endif default: generate_exception_end(ctx, EXCP_RI); break; - } + } + tcg_temp_free(t0); + tcg_temp_free(v1_t); } + static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) { int rt = (ctx->opcode >> 21) & 0x1f; int rs = (ctx->opcode >> 16) & 0x1f; + int rd = (ctx->opcode >> 11) & 0x1f; switch ((ctx->opcode >> 6) & 0x07) { + case NM_POOL32AXF_1: + { + int32_t op1 = (ctx->opcode >> 9) & 0x07; + gen_pool32axf_1_nanomips_insn(ctx, op1, rt, rs, rd); + } + break; + case NM_POOL32AXF_2: + { + int32_t op1 = (ctx->opcode >> 12) & 0x03; + gen_pool32axf_2_nanomips_insn(ctx, op1, rt, rs, rd); + } + break; case NM_POOL32AXF_4: + { + int32_t op1 = (ctx->opcode >> 9) & 0x7f; + gen_pool32axf_4_nanomips_insn(ctx, op1, rt, rs, rd); + } + break; case NM_POOL32AXF_5: switch ((ctx->opcode >> 9) & 0x7f) { case NM_CLO: @@ -16946,6 +18212,12 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) break; } break; + case NM_POOL32AXF_7: + { + int32_t op1 = (ctx->opcode >> 9) & 0x7; + gen_pool32axf_7_nanomips_insn(ctx, op1, rt, rs, rd); + } + break; default: generate_exception_end(ctx, EXCP_RI); break; @@ -17609,6 +18881,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) case NM_POOL32A0: gen_pool32a0_nanomips_insn(env, ctx); break; + case NM_POOL32A5: + { + int32_t op1 = (ctx->opcode >> 3) & 0x7F; + gen_pool32a5_nanomips_insn(ctx, op1, rd, rs, rt); + } + break; case NM_POOL32A7: { switch ((ctx->opcode >> 3) & 0x07) { @@ -18249,6 +19527,18 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) case NM_BC1NEZC: gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rt, s, 0); break; + case NM_BPOSGE32C: + check_dsp(ctx); + { + int32_t imm = ctx->opcode; + imm >>= 1; + imm &= 0x1fff; + imm |= (ctx->opcode & 1) << 13; + + gen_compute_branch(ctx, OPC_BPOSGE32, 4, -1, -2, + (int32_t)imm, 4); + } + break; default: generate_exception_end(ctx, EXCP_RI); break; From patchwork Thu Jul 19 12:54:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946343 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Wb8s5PGkz9s4r for ; Thu, 19 Jul 2018 23:54:05 +1000 (AEST) Received: from localhost ([::1]:43090 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9Nb-0006k6-7a for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:54:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51446) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Wh-0003Os-F7 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:00:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Vd-0006Ud-Dm for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:23 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57545 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8Vc-0006T9-RL for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:58:17 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 35ADE1A4164; Thu, 19 Jul 2018 14:58:15 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 190C11A1D42; Thu, 19 Jul 2018 14:58:15 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:54 +0200 Message-Id: <1532004912-13899-23-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 22/40] target/mips: Add handling of branch delay slots for nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Matthew Fortune ISA mode bit (LSB of address) is no longer required but is also masked to allow for tools transition. The flag has_isa_mode has the key role in the implementation. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index d7454a6..7fb2ff9 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1458,6 +1458,7 @@ typedef struct DisasContext { bool mrp; bool nan2008; bool abs2008; + bool has_isa_mode; } DisasContext; #define DISAS_STOP DISAS_TARGET_0 @@ -4538,7 +4539,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, if (blink > 0) { int post_delay = insn_bytes + delayslot_size; - int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16); + int lowbit = ctx->has_isa_mode && !!(ctx->hflags & MIPS_HFLAG_M16); tcg_gen_movi_tl(cpu_gpr[blink], ctx->base.pc_next + post_delay + lowbit); @@ -10991,7 +10992,8 @@ static void gen_branch(DisasContext *ctx, int insn_bytes) break; case MIPS_HFLAG_BR: /* unconditional branch to register */ - if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) { + if (ctx->has_isa_mode && + (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS))) { TCGv t0 = tcg_temp_new(); TCGv_i32 t1 = tcg_temp_new_i32(); @@ -11027,7 +11029,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, int bcond_compute = 0; TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); - int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0; + int m16_lowbit = ctx->has_isa_mode && ((ctx->hflags & MIPS_HFLAG_M16) != 0); if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS @@ -24747,6 +24749,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1; ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; + ctx->has_isa_mode = ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) != 3; restore_cpu_state(env, ctx); #ifdef CONFIG_USER_ONLY ctx->mem_idx = MIPS_HFLAG_UM; From patchwork Thu Jul 19 12:54:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946394 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Wbdp2b00z9s4r for ; Fri, 20 Jul 2018 00:15:40 +1000 (AEST) Received: from localhost ([::1]:43363 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9iT-00015v-MC for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:15:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56395) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Zi-0004Rx-Fc for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:05:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Vl-0006YA-8h for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:02:30 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57580 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8Vk-0006XY-KM for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:58:25 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 0DD4E1A1D42; Thu, 19 Jul 2018 14:58:23 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id D51CF1A456D; Thu, 19 Jul 2018 14:58:22 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:55 +0200 Message-Id: <1532004912-13899-24-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 23/40] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Implement nanoMIPS LLWP and SCWP instruction pair. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- linux-user/mips/cpu_loop.c | 25 ++++++++--- target/mips/cpu.h | 2 + target/mips/helper.h | 2 + target/mips/op_helper.c | 35 +++++++++++++++ target/mips/translate.c | 107 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 166 insertions(+), 5 deletions(-) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 084ad6a..1d3dc9e 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -397,10 +397,13 @@ static int do_store_exclusive(CPUMIPSState *env) target_ulong addr; target_ulong page_addr; target_ulong val; + uint32_t val_wp = 0; + uint32_t llnewval_wp = 0; int flags; int segv = 0; int reg; int d; + int wp; addr = env->lladdr; page_addr = addr & TARGET_PAGE_MASK; @@ -412,19 +415,31 @@ static int do_store_exclusive(CPUMIPSState *env) } else { reg = env->llreg & 0x1f; d = (env->llreg & 0x20) != 0; - if (d) { - segv = get_user_s64(val, addr); + wp = (env->llreg & 0x40) != 0; + if (!wp) { + if (d) { + segv = get_user_s64(val, addr); + } else { + segv = get_user_s32(val, addr); + } } else { segv = get_user_s32(val, addr); + segv |= get_user_s32(val_wp, addr); + llnewval_wp = env->llnewval_wp; } if (!segv) { - if (val != env->llval) { + if (val != env->llval && val_wp == llnewval_wp) { env->active_tc.gpr[reg] = 0; } else { - if (d) { - segv = put_user_u64(env->llnewval, addr); + if (!wp) { + if (d) { + segv = put_user_u64(env->llnewval, addr); + } else { + segv = put_user_u32(env->llnewval, addr); + } } else { segv = put_user_u32(env->llnewval, addr); + segv |= put_user_u32(env->llnewval_wp, addr + 4); } if (!segv) { env->active_tc.gpr[reg] = 1; diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 009202c..2d341d7 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -506,6 +506,8 @@ struct CPUMIPSState { uint64_t lladdr; target_ulong llval; target_ulong llnewval; + uint32_t llval_wp; + uint32_t llnewval_wp; target_ulong llreg; uint64_t CP0_LLAddr_rw_bitmask; int CP0_LLAddr_shift; diff --git a/target/mips/helper.h b/target/mips/helper.h index b2a780a..deca307 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -14,6 +14,8 @@ DEF_HELPER_4(swr, void, env, tl, tl, int) #ifndef CONFIG_USER_ONLY DEF_HELPER_3(ll, tl, env, tl, int) DEF_HELPER_4(sc, tl, env, tl, tl, int) +DEF_HELPER_5(llwp, void, env, tl, i32, i32, i32) +DEF_HELPER_4(scwp, tl, env, tl, i64, int) #ifdef TARGET_MIPS64 DEF_HELPER_3(lld, tl, env, tl, int) DEF_HELPER_4(scd, tl, env, tl, tl, int) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index b3eef9f..cb83b6d 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -380,6 +380,19 @@ HELPER_LD_ATOMIC(lld, ld, 0x7) #endif #undef HELPER_LD_ATOMIC +void helper_llwp(CPUMIPSState *env, target_ulong addr, uint32_t reg1, + uint32_t reg2, uint32_t mem_idx) +{ + if (addr & 0x7) { + env->CP0_BadVAddr = addr; + do_raise_exception(env, EXCP_AdEL, GETPC()); + } + env->lladdr = do_translate_address(env, addr, 0, GETPC()); + env->active_tc.gpr[reg1] = env->llval = do_lw(env, addr, mem_idx, GETPC()); + env->active_tc.gpr[reg2] = env->llval_wp = do_lw(env, addr + 4, mem_idx, + GETPC()); +} + #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \ target_ulong arg2, int mem_idx) \ @@ -406,6 +419,28 @@ HELPER_ST_ATOMIC(sc, lw, sw, 0x3) HELPER_ST_ATOMIC(scd, ld, sd, 0x7) #endif #undef HELPER_ST_ATOMIC + +target_ulong helper_scwp(CPUMIPSState *env, target_ulong addr, + uint64_t data, int mem_idx) +{ + uint32_t tmp; + uint32_t tmp2; + + if (addr & 0x7) { + env->CP0_BadVAddr = addr; + do_raise_exception(env, EXCP_AdES, GETPC()); + } + if (do_translate_address(env, addr, 1, GETPC()) == env->lladdr) { + tmp = do_lw(env, addr, mem_idx, GETPC()); + tmp2 = do_lw(env, addr + 4, mem_idx, GETPC()); + if (tmp == env->llval && tmp2 == env->llval_wp) { + do_sw(env, addr, (uint32_t) data, mem_idx, GETPC()); + do_sw(env, addr + 4, (uint32_t) *(&data + 4), mem_idx, GETPC()); + return 1; + } + } + return 0; +} #endif #ifdef TARGET_WORDS_BIGENDIAN diff --git a/target/mips/translate.c b/target/mips/translate.c index 7fb2ff9..3f915e1 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1459,6 +1459,7 @@ typedef struct DisasContext { bool nan2008; bool abs2008; bool has_isa_mode; + bool xnp; } DisasContext; #define DISAS_STOP DISAS_TARGET_0 @@ -2336,6 +2337,44 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_temp_free(t0); } +static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset, + uint32_t reg1, uint32_t reg2) +{ +#ifdef CONFIG_USER_ONLY + TCGv taddr = tcg_temp_new(); + TCGv tval = tcg_temp_new(); + + gen_base_offset_addr(ctx, taddr, base, offset); + tcg_gen_qemu_ld32s(tval, taddr, ctx->mem_idx); + tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr)); + tcg_gen_st_tl(tval, cpu_env, offsetof(CPUMIPSState, llval)); + tcg_gen_ext32s_tl(tval, tval); + gen_store_gpr(tval, reg1); + + gen_base_offset_addr(ctx, taddr, base, offset + 4); + tcg_gen_qemu_ld32s(tval, taddr, ctx->mem_idx); + tcg_gen_st_tl(tval, cpu_env, offsetof(CPUMIPSState, llval_wp)); + tcg_gen_ext32s_tl(tval, tval); + gen_store_gpr(tval, reg2); + + tcg_temp_free(taddr); + tcg_temp_free(tval); +#else + TCGv taddr = tcg_temp_new(); + TCGv_i32 helper_mem_idx = tcg_const_i32(ctx->mem_idx); + TCGv_i32 helper_reg1 = tcg_const_i32(reg1); + TCGv_i32 helper_reg2 = tcg_const_i32(reg2); + + gen_base_offset_addr(ctx, taddr, base, offset); + gen_helper_llwp(cpu_env, taddr, helper_reg1, helper_reg2, helper_mem_idx); + + tcg_temp_free(taddr); + tcg_temp_free_i32(helper_mem_idx); + tcg_temp_free_i32(helper_reg1); + tcg_temp_free_i32(helper_reg2); +#endif +} + /* Store */ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, int base, int offset) @@ -2432,6 +2471,63 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, tcg_temp_free(t0); } +static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, + uint32_t reg1, uint32_t reg2) +{ +#ifdef CONFIG_USER_ONLY + TCGv taddr = tcg_temp_local_new(); + TCGv t0 = tcg_temp_new(); + TCGLabel *l1 = gen_new_label(); + TCGLabel *l2 = gen_new_label(); + + gen_base_offset_addr(ctx, taddr, base, offset); + tcg_gen_andi_tl(t0, taddr, 0x7); + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); + tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); + generate_exception(ctx, EXCP_AdES); + gen_set_label(l1); + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); + tcg_gen_brcond_tl(TCG_COND_NE, taddr, t0, l2); + tcg_gen_movi_tl(t0, reg1 | 0x60); + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llreg)); + gen_load_gpr(t0, reg1); + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llnewval)); + gen_load_gpr(t0, reg2); + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llnewval_wp)); + generate_exception_end(ctx, EXCP_SC); + gen_set_label(l2); + tcg_gen_movi_tl(t0, 0); + gen_store_gpr(t0, reg1); + tcg_temp_free(t0); + tcg_temp_free(taddr); +#else + TCGv taddr = tcg_temp_new(); + TCGv_i64 tdata = tcg_temp_new_i64(); + TCGv_i32 helper_mem_idx = tcg_const_i32(ctx->mem_idx); + + TCGv t0 = tcg_temp_new(); + TCGv_i64 t1_64 = tcg_temp_new_i64(); + + gen_load_gpr(t0, reg2); + tcg_gen_ext_tl_i64(tdata, t0); + tcg_gen_shli_i64(tdata, tdata, 32); + + gen_load_gpr(t0, reg1); + tcg_gen_ext_tl_i64(t1_64, t0); + tcg_gen_or_i64(tdata, tdata, t1_64); + + gen_base_offset_addr(ctx, taddr, base, offset); + gen_helper_scwp(cpu_gpr[reg1], cpu_env, taddr, tdata, helper_mem_idx); + + tcg_temp_free(taddr); + tcg_temp_free_i64(tdata); + tcg_temp_free_i32(helper_mem_idx); + + tcg_temp_free(t0); + tcg_temp_free_i64(t1_64); +#endif +} + /* Load and store */ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, TCGv t0) @@ -19399,6 +19495,11 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_ld(ctx, OPC_LL, rt, rs, s); break; case NM_LLWP: + if (ctx->xnp) { + generate_exception_end(ctx, EXCP_RI); + } else { + gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5)); + } break; } break; @@ -19408,6 +19509,11 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_st_cond(ctx, OPC_SC, rt, rs, s); break; case NM_SCWP: + if (ctx->xnp) { + generate_exception_end(ctx, EXCP_RI); + } else { + gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5)); + } break; } break; @@ -24750,6 +24856,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; ctx->has_isa_mode = ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) != 3; + ctx->xnp = (env->CP0_Config5 >> CP0C5_XNP) & 1; restore_cpu_state(env, ctx); #ifdef CONFIG_USER_ONLY ctx->mem_idx = MIPS_HFLAG_UM; From patchwork Thu Jul 19 12:54:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946381 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbPk1psxz9s5c for ; Fri, 20 Jul 2018 00:05:14 +1000 (AEST) Received: from localhost ([::1]:43220 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9YN-000845-T4 for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:05:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55254) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Z7-0004Mx-0U for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:03:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Vq-0006bW-Q6 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:01:53 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57598 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8Vq-0006ak-60 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:58:30 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id A948A1A4156; Thu, 19 Jul 2018 14:58:28 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 8C9411A22AF; Thu, 19 Jul 2018 14:58:28 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:56 +0200 Message-Id: <1532004912-13899-25-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 24/40] target/mips: Add updating BadInstr and BadInstrP registers for nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Updating BadInstr and BadInstrP registers was addded for nanoMIPS. BadInstr and BadInstrP support for pre-nanoMIPS remains unimplemented. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/helper.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index e215af9..5299f21 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -683,7 +683,28 @@ static void set_hflags_for_handler (CPUMIPSState *env) static inline void set_badinstr_registers(CPUMIPSState *env) { if (env->hflags & MIPS_HFLAG_M16) { - /* TODO: add BadInstr support for microMIPS */ + uint32_t instr; + if (!(env->insn_flags & ISA_NANOMIPS32)) { + /* TODO: add BadInstr support for pre-nanoMIPS */ + return; + } + if (env->CP0_Config3 & (1 << CP0C3_BI)) { + instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16; + if ((env->insn_flags & ISA_NANOMIPS32) && + ((instr & 0x10000000) == 0)) { + instr |= cpu_lduw_code(env, env->active_tc.PC + 2); + } + env->CP0_BadInstr = instr; + } + if ((env->CP0_Config3 & (1 << CP0C3_BP)) && + (env->hflags & MIPS_HFLAG_BMASK)) { + if (!(env->hflags & MIPS_HFLAG_B16)) { + env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4); + } else { + env->CP0_BadInstrP = + (cpu_lduw_code(env, env->active_tc.PC - 2)) << 16; + } + } return; } if (env->CP0_Config3 & (1 << CP0C3_BI)) { From patchwork Thu Jul 19 12:54:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946319 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WZtd6zr2z9s7c for ; Thu, 19 Jul 2018 23:41:44 +1000 (AEST) Received: from localhost ([::1]:43028 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9Bd-0004fQ-O3 for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:41:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55184) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Z0-0004MK-1x for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:02:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Vx-0006gI-6X for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:01:46 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57630 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8Vw-0006fU-QE for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:58:37 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 4F0C41A4577; Thu, 19 Jul 2018 14:58:35 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 328341A4575; Thu, 19 Jul 2018 14:58:35 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:57 +0200 Message-Id: <1532004912-13899-26-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 25/40] target/mips: Add updating CP0 BadInstrX register for nanoMIPs only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Stefan Markovic Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/mips/helper.c b/target/mips/helper.c index 5299f21..9535131 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -695,6 +695,12 @@ static inline void set_badinstr_registers(CPUMIPSState *env) instr |= cpu_lduw_code(env, env->active_tc.PC + 2); } env->CP0_BadInstr = instr; + + if ((env->insn_flags & ISA_NANOMIPS32) && + ((instr & 0xFC000000) == 0x60000000)) { + instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16; + env->CP0_BadInstrX = instr; + } } if ((env->CP0_Config3 & (1 << CP0C3_BP)) && (env->hflags & MIPS_HFLAG_BMASK)) { From patchwork Thu Jul 19 12:54:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946392 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbbV5Jrhz9s4r for ; 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Thu, 19 Jul 2018 14:58:40 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:58 +0200 Message-Id: <1532004912-13899-27-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 26/40] target/mips: Implement CP0 Config0.WR bit functionality X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Stefan Markovic Add testing Config0.WR bit into watch exception handling logic. Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/helper.c | 12 +++++++++++- target/mips/translate.c | 22 ++++++++++++++++------ 2 files changed, 27 insertions(+), 7 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index 9535131..dc8f2a5 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -749,6 +749,14 @@ void mips_cpu_do_interrupt(CPUState *cs) (env->hflags & MIPS_HFLAG_DM)) { cs->exception_index = EXCP_DINT; } + + if ((cs->exception_index == EXCP_DWATCH || + cs->exception_index == EXCP_DFWATCH || + cs->exception_index == EXCP_IWATCH) && + (env->CP0_Config1 & (1 << CP0C1_WR))) { + cs->exception_index = EXCP_NONE; + } + offset = 0x180; switch (cs->exception_index) { case EXCP_DSS: @@ -799,7 +807,9 @@ void mips_cpu_do_interrupt(CPUState *cs) break; case EXCP_SRESET: env->CP0_Status |= (1 << CP0St_SR); - memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo)); + if (env->CP0_Config1 & (1 << CP0C1_WR)) { + memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo)); + } goto set_error_EPC; case EXCP_NMI: env->CP0_Status |= (1 << CP0St_NMI); diff --git a/target/mips/translate.c b/target/mips/translate.c index 3f915e1..ec486bb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5622,6 +5622,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(mfc0_watchlo, arg, sel); rn = "WatchLo"; break; @@ -5639,6 +5640,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(mfc0_watchhi, arg, sel); rn = "WatchHi"; break; @@ -6321,6 +6323,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchlo, arg, sel); rn = "WatchLo"; break; @@ -6338,6 +6341,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchhi, arg, sel); rn = "WatchHi"; break; @@ -7024,6 +7028,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(dmfc0_watchlo, arg, sel); rn = "WatchLo"; break; @@ -7041,6 +7046,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(mfc0_watchhi, arg, sel); rn = "WatchHi"; break; @@ -7705,6 +7711,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchlo, arg, sel); rn = "WatchLo"; break; @@ -7722,6 +7729,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchhi, arg, sel); rn = "WatchHi"; break; @@ -25281,14 +25289,16 @@ void cpu_state_reset(CPUMIPSState *env) no performance counters. */ env->CP0_IntCtl = 0xe0000000; { - int i; + if (env->CP0_Config1 & (1 << CP0C1_WR)) { + int i; - for (i = 0; i < 7; i++) { - env->CP0_WatchLo[i] = 0; - env->CP0_WatchHi[i] = 0x80000000; + for (i = 0; i < 7; i++) { + env->CP0_WatchLo[i] = 0; + env->CP0_WatchHi[i] = 0x80000000; + } + env->CP0_WatchLo[7] = 0; + env->CP0_WatchHi[7] = 0; } - env->CP0_WatchLo[7] = 0; - env->CP0_WatchHi[7] = 0; } /* Count register increments in debug mode, EJTAG version 1 */ env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); From patchwork Thu Jul 19 12:54:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946311 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WZm25Fhxz9s7T for ; Thu, 19 Jul 2018 23:36:01 +1000 (AEST) Received: from localhost ([::1]:43003 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg966-0007pf-NS for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:35:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54995) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Yl-0004Jd-3O for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:03:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8W9-0006ny-4F for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:01:31 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57690 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8W8-0006nS-O2 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:58:48 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 4907A1A4156; Thu, 19 Jul 2018 14:58:47 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 2C8F61A2025; Thu, 19 Jul 2018 14:58:47 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:59 +0200 Message-Id: <1532004912-13899-28-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 27/40] target/mips: Adjust behavior of Config3's ISAOnExc bit for nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Config3.ISAOnExc is read only in nanoMIPS. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/op_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index cb83b6d..5e10286 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1730,7 +1730,8 @@ void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1) { - if (env->insn_flags & ASE_MICROMIPS) { + if ((env->insn_flags & ASE_MICROMIPS) && + !(env->insn_flags & ISA_NANOMIPS32)) { env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) | (arg1 & (1 << CP0C3_ISA_ON_EXC)); } From patchwork Thu Jul 19 12:55:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946366 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbHQ6J0fz9s4r for ; Thu, 19 Jul 2018 23:59:45 +1000 (AEST) Received: from localhost ([::1]:43118 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9T4-0003Lt-2e for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:59:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52776) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8XK-0003dQ-7d for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:02:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8WG-0006rj-7P for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:00:02 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57714 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8WF-0006qv-Qd for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:58:56 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 6A8401A22B2; Thu, 19 Jul 2018 14:58:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 4E86E1A2025; Thu, 19 Jul 2018 14:58:54 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:55:00 +0200 Message-Id: <1532004912-13899-29-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 28/40] target/mips: Adjust exception_resume_pc() for nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: James Hogan We shouldn't set the ISA bit in CP0_EPC for nanoMIPS. Signed-off-by: James Hogan Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index dc8f2a5..fb47018 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -656,7 +656,8 @@ target_ulong exception_resume_pc (CPUMIPSState *env) target_ulong bad_pc; target_ulong isa_mode; - isa_mode = !!(env->hflags & MIPS_HFLAG_M16); + isa_mode = env->hflags & MIPS_HFLAG_M16 && + !(env->insn_flags & ISA_NANOMIPS32); bad_pc = env->active_tc.PC | isa_mode; if (env->hflags & MIPS_HFLAG_BMASK) { /* If the exception was raised from a delay slot, come back to From patchwork Thu Jul 19 12:55:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946387 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbVv0HQTz9s5c for ; Fri, 20 Jul 2018 00:09:43 +1000 (AEST) Received: from localhost ([::1]:43251 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9ci-0003g4-Mk for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:09:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55692) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8ZN-0004P5-DP for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:03:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8WN-0006wZ-Tu for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:02:09 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57760 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8WN-0006vW-Gm for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:03 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 1D45E1A2025; Thu, 19 Jul 2018 14:59:02 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 019C11A1D42; Thu, 19 Jul 2018 14:59:02 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:55:01 +0200 Message-Id: <1532004912-13899-30-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 29/40] target/mips: Adjust set_hflags_for_handler() for nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: James Hogan We shouldn't clear M16 mode when entering an interrupt on nanoMIPS, otherwise we'll start interpreting the code as normal MIPS code. Signed-off-by: James Hogan Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/mips/helper.c b/target/mips/helper.c index fb47018..e5fc981 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -671,6 +671,9 @@ target_ulong exception_resume_pc (CPUMIPSState *env) #if !defined(CONFIG_USER_ONLY) static void set_hflags_for_handler (CPUMIPSState *env) { + if (env->insn_flags & ISA_NANOMIPS32) { + return; + } /* Exception handlers are entered in 32-bit mode. */ env->hflags &= ~(MIPS_HFLAG_M16); /* ...except that microMIPS lets you choose. */ From patchwork Thu Jul 19 12:55:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946376 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbM14BqWz9s4r for ; Fri, 20 Jul 2018 00:02:53 +1000 (AEST) Received: from localhost ([::1]:43197 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9W6-0006AR-Qz for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:02:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53425) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Xf-0003iL-I3 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:03:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8WY-00072k-Vo for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:00:22 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57928 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8WY-00071s-D0 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:14 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 00A891A2025; Thu, 19 Jul 2018 14:59:13 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id D48E21A1D42; Thu, 19 Jul 2018 14:59:12 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:55:02 +0200 Message-Id: <1532004912-13899-31-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 30/40] target/mips: Adjust set_pc() for nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: James Hogan ERET and ERETNC shouldn't clear MIPS_HFLAG_M16 for nanoMIPS since there is no ISA bit, so fix set_pc() to skip the hflags update. Signed-off-by: James Hogan Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic --- target/mips/op_helper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 5e10286..c55a1e6 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2428,6 +2428,10 @@ static void debug_post_eret(CPUMIPSState *env) static void set_pc(CPUMIPSState *env, target_ulong error_pc) { env->active_tc.PC = error_pc & ~(target_ulong)1; + if (env->insn_flags & ISA_NANOMIPS32) { + /* Don't clear MIPS_HFLAG_M16 */ + return; + } if (error_pc & 1) { env->hflags |= MIPS_HFLAG_M16; } else { From patchwork Thu Jul 19 12:55:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946380 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbPQ1wWsz9s8f for ; Fri, 20 Jul 2018 00:04:58 +1000 (AEST) Received: from localhost ([::1]:43218 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9Y7-0007oO-TI for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:04:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55852) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8ZS-0004Q2-Tp for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:03:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Wf-00075N-ET for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:02:14 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57963 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8We-00074z-UN for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:21 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 659641A4156; Thu, 19 Jul 2018 14:59:19 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 49D891A1D42; Thu, 19 Jul 2018 14:59:19 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:55:03 +0200 Message-Id: <1532004912-13899-32-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 31/40] target/mips: Fix ERET/ERETNC behavior related to ADEL exception X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Yongbok Kim Fix ERET/ERETNC so that ADEL exception can be raised. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic --- target/mips/op_helper.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index c55a1e6..e6749c5 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2430,6 +2430,13 @@ static void set_pc(CPUMIPSState *env, target_ulong error_pc) env->active_tc.PC = error_pc & ~(target_ulong)1; if (env->insn_flags & ISA_NANOMIPS32) { /* Don't clear MIPS_HFLAG_M16 */ + if (error_pc & 1) { + if (!(env->hflags & MIPS_HFLAG_DM)) { + env->CP0_BadVAddr = error_pc; + } + env->active_tc.PC = error_pc; + do_raise_exception(env, EXCP_AdEL, 0); + } return; } if (error_pc & 1) { @@ -2467,10 +2474,12 @@ void helper_eretnc(CPUMIPSState *env) void helper_deret(CPUMIPSState *env) { debug_pre_eret(env); - set_pc(env, env->CP0_DEPC); env->hflags &= ~MIPS_HFLAG_DM; compute_hflags(env); + + set_pc(env, env->CP0_DEPC); + debug_post_eret(env); } #endif /* !CONFIG_USER_ONLY */ From patchwork Thu Jul 19 12:55:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946355 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbDD3bVXz9s4r for ; Thu, 19 Jul 2018 23:57:00 +1000 (AEST) Received: from localhost ([::1]:43107 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9QP-00016d-VP for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:56:58 -0400 Received: from eggs.gnu.org ([208.118.235.92]:52078) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8ao-00051c-Of for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:05:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Wm-0007Ad-OL for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:03:38 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57985 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8Wm-00079E-7l for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:28 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id A97271A2025; Thu, 19 Jul 2018 14:59:25 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 8C17E1A1D42; Thu, 19 Jul 2018 14:59:25 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:55:04 +0200 Message-Id: <1532004912-13899-33-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 32/40] elf: Add nanoMIPS specific variations in ELF header fields X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Add nanoMIPS-related values in ELF header fields as specified in nanoMIPS' "ELF ABI Supplement". Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Acked-by: Richard Henderson --- include/elf.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/elf.h b/include/elf.h index 2c4fe7a..fff5967 100644 --- a/include/elf.h +++ b/include/elf.h @@ -62,6 +62,24 @@ typedef int64_t Elf64_Sxword; #define EF_MIPS_NAN2008 0x00000400 #define EF_MIPS_ARCH 0xf0000000 +/* nanoMIPS architecture bits, EF_NANOMIPS_ARCH */ +#define EF_NANOMIPS_ARCH_32R6 0x00000000 /* 32-bit nanoMIPS Release 6 ISA */ +#define EF_NANOMIPS_ARCH_64R6 0x10000000 /* 62-bit nanoMIPS Release 6 ISA */ + +/* nanoMIPS ABI bits, EF_NANOMIPS_ABI */ +#define EF_NANOMIPS_ABI_P32 0x00001000 /* 32-bit nanoMIPS ABI */ +#define EF_NANOMIPS_ABI_P64 0x00002000 /* 64-bit nanoMIPS ABI */ + +/* nanoMIPS processor specific flags, e_flags */ +#define EF_NANOMIPS_LINKRELAX 0x00000001 /* Link-time relaxation */ +#define EF_NANOMIPS_PIC 0x00000002 /* Position independant code */ +#define EF_NANOMIPS_32BITMODE 0x00000004 /* 32-bit object for 64-bit arch. */ +#define EF_NANOMIPS_PID 0x00000008 /* Position independant data */ +#define EF_NANOMIPS_PCREL 0x00000010 /* PC-relative mode */ +#define EF_NANOMIPS_ABI 0x0000f000 /* nanoMIPS ABI */ +#define EF_NANOMIPS_MACH 0x00ff0000 /* Machine variant */ +#define EF_NANOMIPS_ARCH 0xf0000000 /* nanoMIPS architecture */ + /* MIPS machine variant */ #define EF_MIPS_MACH_NONE 0x00000000 /* A standard MIPS implementation */ #define EF_MIPS_MACH_3900 0x00810000 /* Toshiba R3900 */ @@ -143,6 +161,8 @@ typedef int64_t Elf64_Sxword; #define EM_RISCV 243 /* RISC-V */ +#define EM_NANOMIPS 249 /* Wave Computing nanoMIPS */ + /* * This is an interim value that we will use until the committee comes * up with a final number. From patchwork Thu Jul 19 12:55:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946384 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbSP0VNTz9s4r for ; Fri, 20 Jul 2018 00:07:32 +1000 (AEST) Received: from localhost ([::1]:43241 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9ac-0001xU-HR for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:07:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55951) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8ZW-0004Q7-0m for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:03:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Wu-0007Eo-0k for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:02:18 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:58034 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8Wt-0007EG-Gg for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:35 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 22E891A4577; Thu, 19 Jul 2018 14:59:34 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 0736C1A455F; Thu, 19 Jul 2018 14:59:34 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:55:05 +0200 Message-Id: <1532004912-13899-34-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 33/40] elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Starting from nanoMIPS introduction, machine variant can be EM_MIPS or EM_NANOMIPS. Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Richard Henderson --- linux-user/elfload.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 942a1b6..1900556 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -853,6 +853,8 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUPPCState *en #endif #define ELF_ARCH EM_MIPS +#define elf_check_arch(x) ((x) == EM_MIPS || (x) == EM_NANOMIPS) + static inline void init_thread(struct target_pt_regs *regs, struct image_info *infop) { From patchwork Thu Jul 19 12:55:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946344 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41Wb8s5bqbz9s55 for ; Thu, 19 Jul 2018 23:54:05 +1000 (AEST) Received: from localhost ([::1]:43089 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9Nb-0006jo-EW for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:54:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55584) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8ZK-0004Op-2w for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:05:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Wz-0007Hb-C1 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:02:06 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:58051 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8Wy-0007Gw-Qo for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:41 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 71C241A44FF; Thu, 19 Jul 2018 14:59:39 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 558DC1A1D42; Thu, 19 Jul 2018 14:59:39 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:55:06 +0200 Message-Id: <1532004912-13899-35-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 34/40] linux-user: Don't check FCR31_NAN2008 bit for nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Richard Henderson --- linux-user/mips/cpu_loop.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 1d3dc9e..c9c20cf 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -747,6 +747,9 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) if (regs->cp0_epc & 1) { env->hflags |= MIPS_HFLAG_M16; } + if (env->insn_flags & ISA_NANOMIPS32) { + return; + } if (((info->elf_flags & EF_MIPS_NAN2008) != 0) != ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) { if ((env->active_fpu.fcr31_rw_bitmask & From patchwork Thu Jul 19 12:55:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946367 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbHX4WrDz9s4r for ; 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Thu, 19 Jul 2018 14:59:44 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:55:07 +0200 Message-Id: <1532004912-13899-36-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 35/40] mips_malta: Add basic nanoMIPS boot code for MIPS' Malta X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Matthew Fortune Added very very basic nanoMIPS boot code but this is hacked in unconditionally currently. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- hw/mips/mips_malta.c | 75 +++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 69 insertions(+), 6 deletions(-) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 3467451..4bc9036 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -620,6 +620,58 @@ static void network_init(PCIBus *pci_bus) a2 - 32-bit address of the environment variables table a3 - RAM size in bytes */ +static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr, + int64_t kernel_entry) +{ + uint16_t *p; + + /* Small bootloader */ + p = (uint16_t *)base; + +#define NM_HI1(VAL) (((VAL) >> 16) & 0x1f) +#define NM_HI2(VAL) \ + (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1)) +#define NM_LO(VAL) ((VAL) & 0xfff) + + stw_p(p++, 0x2800); stw_p(p++, 0x001c); /* bc to_here */ + stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ + stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ + stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ + stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ + stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ + stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ + stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ + + /* to_here: */ + stw_p(p++, 0x0080); stw_p(p++, 0x0002); /* li a0,2 */ + stw_p(p++, 0xe3a0 | NM_HI1(ENVP_ADDR - 64)); + stw_p(p++, NM_HI2(ENVP_ADDR - 64)); + /* lui sp,%hi(ENVP_ADDR - 64) */ + stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_ADDR - 64)); + /* ori sp,sp,%lo(ENVP_ADDR - 64) */ + stw_p(p++, 0xe0a0 | NM_HI1(ENVP_ADDR)); + stw_p(p++, NM_HI2(ENVP_ADDR)); + /* lui a1,%hi(ENVP_ADDR) */ + stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_ADDR)); + /* ori a1,a1,%lo(ENVP_ADDR) */ + stw_p(p++, 0xe0c0 | NM_HI1(ENVP_ADDR + 8)); + stw_p(p++, NM_HI2(ENVP_ADDR + 8)); + /* lui a2,%hi(ENVP_ADDR + 8) */ + stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_ADDR + 8)); + /* ori a2,a2,%lo(ENVP_ADDR + 8) */ + stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size)); + stw_p(p++, NM_HI2(loaderparams.ram_low_size)); + /* lui a3,%hi(loaderparams.ram_low_size) */ + stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size)); + /* ori a3,a3,%lo(loaderparams.ram_low_size) */ + stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); + stw_p(p++, NM_HI2(kernel_entry)); + /* lui t9,%hi(kernel_entry) */ + stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry)); + /* ori t9,t9,%lo(kernel_entry) */ + stw_p(p++, 0x4bf9); stw_p(p++, 0x0000); + /* jalrc t8 */ +} static void write_bootloader(uint8_t *base, int64_t run_addr, int64_t kernel_entry) @@ -813,10 +865,16 @@ static int64_t load_kernel (void) NULL, (uint64_t *)&kernel_entry, NULL, (uint64_t *)&kernel_high, big_endian, EM_MIPS, 1, 0); if (kernel_size < 0) { - error_report("could not load kernel '%s': %s", - loaderparams.kernel_filename, - load_elf_strerror(kernel_size)); - exit(1); + kernel_size = load_elf(loaderparams.kernel_filename, + cpu_mips_kseg0_to_phys, NULL, + (uint64_t *)&kernel_entry, NULL, + (uint64_t *)&kernel_high, big_endian, EM_NANOMIPS, 1, 0); + if (kernel_size < 0) { + error_report("could not load kernel '%s': %s", + loaderparams.kernel_filename, + load_elf_strerror(kernel_size)); + exit(1); + } } /* Check where the kernel has been linked */ @@ -1096,8 +1154,13 @@ void mips_malta_init(MachineState *machine) loaderparams.initrd_filename = initrd_filename; kernel_entry = load_kernel(); - write_bootloader(memory_region_get_ram_ptr(bios), - bootloader_run_addr, kernel_entry); + if (!cpu_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { + write_bootloader(memory_region_get_ram_ptr(bios), + bootloader_run_addr, kernel_entry); + } else { + write_bootloader_nanomips(memory_region_get_ram_ptr(bios), + bootloader_run_addr, kernel_entry); + } if (kvm_enabled()) { /* Write the bootloader code @ the end of RAM, 1MB reserved */ write_bootloader(memory_region_get_ram_ptr(ram_low_preio) + From patchwork Thu Jul 19 12:55:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946375 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbLc2l5Xz9s4r for ; Fri, 20 Jul 2018 00:02:32 +1000 (AEST) Received: from localhost ([::1]:43194 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9Vm-0005pW-1G for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:02:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54443) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8YG-0004FK-5y for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:03:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8XC-0007QB-3N for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:01:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:58130 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8XB-0007Ou-Cp for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:53 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 1004A1A242C; Thu, 19 Jul 2018 14:59:51 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id E5CA71A1D42; Thu, 19 Jul 2018 14:59:50 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:55:08 +0200 Message-Id: <1532004912-13899-37-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 36/40] mips_malta: Setup GT64120 BARs in nanoMIPS bootloader X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Paul Burton Setup the GT64120 BARs in the nanoMIPS bootloader, in the same way that they are setup in the MIPS32 bootloader. This is necessary for Linux to be able to access peripherals, including the UART. Signed-off-by: Paul Burton Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic --- hw/mips/mips_malta.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 4bc9036..d1a7c1f 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -664,6 +664,79 @@ static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr, /* lui a3,%hi(loaderparams.ram_low_size) */ stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size)); /* ori a3,a3,%lo(loaderparams.ram_low_size) */ + + /* Load BAR registers as done by YAMON */ + stw_p(p++, 0xe040); stw_p(p++, 0x0681); + /* lui t1, %hi(0xb4000000) */ +#ifdef TARGET_WORDS_BIGENDIAN + stw_p(p++, 0xe020); stw_p(p++, 0x0be1); + /* lui t0, %hi(0xdf000000) */ +#else + stw_p(p++, 0x0020); stw_p(p++, 0x00df); + /* addiu[32] t0, $0, 0xdf */ +#endif + stw_p(p++, 0x8422); stw_p(p++, 0x9068); + /* sw t0, 0x68(t1) */ + + stw_p(p++, 0xe040); stw_p(p++, 0x077d); + /* lui t1, %hi(0xbbe00000) */ +#ifdef TARGET_WORDS_BIGENDIAN + stw_p(p++, 0xe020); stw_p(p++, 0x0801); + /* lui t0, %hi(0xc0000000) */ +#else + stw_p(p++, 0x0020); stw_p(p++, 0x00c0); + /* addiu[32] t0, $0, 0xc0 */ +#endif + stw_p(p++, 0x8422); stw_p(p++, 0x9048); + /* sw t0, 0x48(t1) */ +#ifdef TARGET_WORDS_BIGENDIAN + stw_p(p++, 0xe020); stw_p(p++, 0x0800); + /* lui t0, %hi(0x40000000) */ +#else + stw_p(p++, 0x0020); stw_p(p++, 0x0040); + /* addiu[32] t0, $0, 0x40 */ +#endif + stw_p(p++, 0x8422); stw_p(p++, 0x9050); + /* sw t0, 0x50(t1) */ + +#ifdef TARGET_WORDS_BIGENDIAN + stw_p(p++, 0xe020); stw_p(p++, 0x0001); + /* lui t0, %hi(0x80000000) */ +#else + stw_p(p++, 0x0020); stw_p(p++, 0x0080); + /* addiu[32] t0, $0, 0x80 */ +#endif + stw_p(p++, 0x8422); stw_p(p++, 0x9058); + /* sw t0, 0x58(t1) */ +#ifdef TARGET_WORDS_BIGENDIAN + stw_p(p++, 0xe020); stw_p(p++, 0x07e0); + /* lui t0, %hi(0x3f000000) */ +#else + stw_p(p++, 0x0020); stw_p(p++, 0x003f); + /* addiu[32] t0, $0, 0x3f */ +#endif + stw_p(p++, 0x8422); stw_p(p++, 0x9060); + /* sw t0, 0x60(t1) */ + +#ifdef TARGET_WORDS_BIGENDIAN + stw_p(p++, 0xe020); stw_p(p++, 0x0821); + /* lui t0, %hi(0xc1000000) */ +#else + stw_p(p++, 0x0020); stw_p(p++, 0x00c1); + /* addiu[32] t0, $0, 0xc1 */ +#endif + stw_p(p++, 0x8422); stw_p(p++, 0x9080); + /* sw t0, 0x80(t1) */ +#ifdef TARGET_WORDS_BIGENDIAN + stw_p(p++, 0xe020); stw_p(p++, 0x0bc0); + /* lui t0, %hi(0x5e000000) */ +#else + stw_p(p++, 0x0020); stw_p(p++, 0x005e); + /* addiu[32] t0, $0, 0x5e */ +#endif + stw_p(p++, 0x8422); stw_p(p++, 0x9088); + /* sw t0, 0x88(t1) */ + stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); stw_p(p++, NM_HI2(kernel_entry)); /* lui t9,%hi(kernel_entry) */ From patchwork Thu Jul 19 12:55:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946383 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbS26BRhz9s5c for ; Fri, 20 Jul 2018 00:07:14 +1000 (AEST) Received: from localhost ([::1]:43237 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9aK-0001j2-EG for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:07:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56794) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Zu-0004ZX-Hk for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:04:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8XQ-0007YW-RA for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:02:42 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:58280 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8XQ-0007Wj-4f for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:00:08 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 8EAC61A4549; Thu, 19 Jul 2018 15:00:06 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 729881A4546; Thu, 19 Jul 2018 15:00:06 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:55:09 +0200 Message-Id: <1532004912-13899-38-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 37/40] mips_malta: Fix semihosting argument passing for nanoMIPS bare metal X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Stefan Markovic Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- hw/mips/mips_malta.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index d1a7c1f..8bb1686 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -643,7 +643,12 @@ static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr, stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ /* to_here: */ - stw_p(p++, 0x0080); stw_p(p++, 0x0002); /* li a0,2 */ + if (semihosting_get_argc()) { + /* Preserve a0 content as arguments have been passed */ + stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */ + } else { + stw_p(p++, 0x0080); stw_p(p++, 0x0002); /* li a0,2 */ + } stw_p(p++, 0xe3a0 | NM_HI1(ENVP_ADDR - 64)); stw_p(p++, NM_HI2(ENVP_ADDR - 64)); /* lui sp,%hi(ENVP_ADDR - 64) */ From patchwork Thu Jul 19 12:55:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946391 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbYL5FS4z9s4r for ; Fri, 20 Jul 2018 00:11:50 +1000 (AEST) Received: from localhost ([::1]:43266 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9em-0005vc-Bj for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:11:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56393) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Zi-0004Rw-EF for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:04:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8XY-0007d4-GR for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:02:30 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:58358 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8XX-0007c4-FC for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:00:15 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id C608F1A4156; Thu, 19 Jul 2018 15:00:13 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id A95771A1D42; Thu, 19 Jul 2018 15:00:13 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:55:10 +0200 Message-Id: <1532004912-13899-39-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 38/40] gdbstub: Disable handling of nanoMIPS ISA bit in the MIPS gdbstub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: James Hogan nanoMIPS has no ISA bit in the PC, so remove the handling of the low bit of the PC in the MIPS gdbstub for nanoMIPS. This prevents the PC being read as e.g. 0xbfc00001, and prevents writing to the PC clearing MIPS_HFLAG_M16. Signed-off-by: James Hogan Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/gdbstub.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index 18e0e6d..559b69f 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -60,7 +60,8 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause); case 37: return gdb_get_regl(mem_buf, env->active_tc.PC | - !!(env->hflags & MIPS_HFLAG_M16)); + (!(env->insn_flags & ISA_NANOMIPS32) && + env->hflags & MIPS_HFLAG_M16)); case 72: return gdb_get_regl(mem_buf, 0); /* fp */ case 89: @@ -131,10 +132,12 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) break; case 37: env->active_tc.PC = tmp & ~(target_ulong)1; - if (tmp & 1) { - env->hflags |= MIPS_HFLAG_M16; - } else { - env->hflags &= ~(MIPS_HFLAG_M16); + if (!(env->insn_flags & ISA_NANOMIPS32)) { + if (tmp & 1) { + env->hflags |= MIPS_HFLAG_M16; + } else { + env->hflags &= ~(MIPS_HFLAG_M16); + } } break; case 72: /* fp, ignored */ From patchwork Thu Jul 19 12:55:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946386 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbVY70d9z9s4r for ; Fri, 20 Jul 2018 00:09:25 +1000 (AEST) Received: from localhost ([::1]:43249 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9cR-0003Sh-JB for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:09:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55007) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Yl-0004Kh-Tf for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:04:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Xh-0007jf-Mt for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:01:31 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:58405 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8Xf-0007h1-QM for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:00:24 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id E7FFA1A4544; Thu, 19 Jul 2018 15:00:21 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id C87051A1D42; Thu, 19 Jul 2018 15:00:21 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:55:11 +0200 Message-Id: <1532004912-13899-40-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 39/40] gdbstub: Add XML support for GDB for nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Stefan Markovic Add XML support files for GDB for nanoMIPS. Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- MAINTAINERS | 3 ++- gdb-xml/nanomips-cp0.xml | 13 +++++++++++++ gdb-xml/nanomips-cpu.xml | 44 ++++++++++++++++++++++++++++++++++++++++++++ gdb-xml/nanomips-dsp.xml | 20 ++++++++++++++++++++ gdb-xml/nanomips-fpu.xml | 45 +++++++++++++++++++++++++++++++++++++++++++++ gdb-xml/nanomips-linux.xml | 20 ++++++++++++++++++++ 6 files changed, 144 insertions(+), 1 deletion(-) create mode 100644 gdb-xml/nanomips-cp0.xml create mode 100644 gdb-xml/nanomips-cpu.xml create mode 100644 gdb-xml/nanomips-dsp.xml create mode 100644 gdb-xml/nanomips-fpu.xml create mode 100644 gdb-xml/nanomips-linux.xml diff --git a/MAINTAINERS b/MAINTAINERS index 7130807..a4907d0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -190,6 +190,8 @@ M: Aurelien Jarno M: Aleksandar Markovic S: Maintained F: target/mips/ +F: disas/mips.c +F: gdb-xml/*ips*.xml F: hw/mips/ F: hw/misc/mips_* F: hw/intc/mips_gic.c @@ -199,7 +201,6 @@ F: include/hw/misc/mips_* F: include/hw/intc/mips_gic.h F: include/hw/timer/mips_gictimer.h F: tests/tcg/mips/ -F: disas/mips.c Moxie M: Anthony Green diff --git a/gdb-xml/nanomips-cp0.xml b/gdb-xml/nanomips-cp0.xml new file mode 100644 index 0000000..8095dc6 --- /dev/null +++ b/gdb-xml/nanomips-cp0.xml @@ -0,0 +1,13 @@ + + + + + + + + + diff --git a/gdb-xml/nanomips-cpu.xml b/gdb-xml/nanomips-cpu.xml new file mode 100644 index 0000000..6bba224 --- /dev/null +++ b/gdb-xml/nanomips-cpu.xml @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/nanomips-dsp.xml b/gdb-xml/nanomips-dsp.xml new file mode 100644 index 0000000..950910f --- /dev/null +++ b/gdb-xml/nanomips-dsp.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + diff --git a/gdb-xml/nanomips-fpu.xml b/gdb-xml/nanomips-fpu.xml new file mode 100644 index 0000000..fd225a5 --- /dev/null +++ b/gdb-xml/nanomips-fpu.xml @@ -0,0 +1,45 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/nanomips-linux.xml b/gdb-xml/nanomips-linux.xml new file mode 100644 index 0000000..8a04634 --- /dev/null +++ b/gdb-xml/nanomips-linux.xml @@ -0,0 +1,20 @@ + + + + + + nanomips + GNU/Linux + + + + + + + + + From patchwork Thu Jul 19 12:55:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Markovic X-Patchwork-Id: 946390 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WbY303Nqz9s7T for ; Fri, 20 Jul 2018 00:11:35 +1000 (AEST) Received: from localhost ([::1]:43264 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9eW-0005j3-MO for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 10:11:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56782) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8Zu-0004ZK-2q for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:04:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Xp-0007sy-U6 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:02:42 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:58630 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8Xo-0007qL-KT for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:00:33 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 1FEA01A2025; Thu, 19 Jul 2018 15:00:31 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 034E41A1D42; Thu, 19 Jul 2018 15:00:31 +0200 (CEST) From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:55:12 +0200 Message-Id: <1532004912-13899-41-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 40/40] target/mips: Add definition of nanoMIPS I7200 CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Stefan Markovic Add definition of the first nanoMIPS processor in QEMU. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate_init.inc.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c index c7ba6ee..d3f32e8 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -449,6 +449,46 @@ const mips_def_t mips_defs[] = .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS, .mmu_type = MMU_TYPE_R4000, }, + { + .name = "I7200", + .CP0_PRid = 0x00010000, + .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) | + (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) | + (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | + (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) | + (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) | + (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) | + (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | + (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | + (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) | + (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL), + .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | + (2 << CP0C4_IE) | (1U << CP0C4_M), + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB), + .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | + (1 << CP0C5_UFE), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x3158FF1F, + .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | + (1U << CP0PG_RIE), + .CP0_PageGrain_rw_bitmask = 0, + .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_NANOMIPS32 | ASE_MICROMIPS | ASE_DSP | ASE_DSPR2 | + ASE_MT, + .mmu_type = MMU_TYPE_R4000, + }, #if defined(TARGET_MIPS64) { .name = "R4000",