Message ID | 1532004912-13899-2-git-send-email-stefan.markovic@rt-rk.com |
---|---|
State | New |
Headers | show
Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41WZm25FCSz9s55 for <incoming@patchwork.ozlabs.org>; Thu, 19 Jul 2018 23:36:01 +1000 (AEST) Received: from localhost ([::1]:43002 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>) id 1fg964-0007pR-ST for incoming@patchwork.ozlabs.org; Thu, 19 Jul 2018 09:35:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49211) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from <stefan.markovic@rt-rk.com>) id 1fg8Vd-0003Br-Ox for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from <stefan.markovic@rt-rk.com>) id 1fg8Sv-00042r-Pd for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:58:17 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:55215 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from <stefan.markovic@rt-rk.com>) id 1fg8Sv-00041p-D6 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:55:29 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id DC19D1A4156; Thu, 19 Jul 2018 14:55:27 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id BF9B91A1D42; Thu, 19 Jul 2018 14:55:27 +0200 (CEST) From: Stefan Markovic <stefan.markovic@rt-rk.com> To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:33 +0200 Message-Id: <1532004912-13899-2-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 01/40] target/mips: Add preprocessor constants for nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> |
Series |
Add nanoMIPS support to QEMU
|
expand
|
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index d239069..c8e9979 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -39,6 +39,7 @@ #define ISA_MIPS64R5 0x00001000 #define ISA_MIPS32R6 0x00002000 #define ISA_MIPS64R6 0x00004000 +#define ISA_NANOMIPS32 0x00008000 /* MIPS ASEs. */ #define ASE_MIPS16 0x00010000 @@ -87,6 +88,9 @@ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) +/* Wave Computing: "nanoMIPS" */ +#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) + /* Strictly follow the architecture standard: - Disallow "special" instruction handling for PMON/SPIM. Note that we still maintain Count/Compare to match the host clock. */