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[v3,25/40] target/mips: Add updating CP0 BadInstrX register for nanoMIPs only

Message ID 1532004912-13899-26-git-send-email-stefan.markovic@rt-rk.com
State New
Headers show
Series Add nanoMIPS support to QEMU | expand

Commit Message

Stefan Markovic July 19, 2018, 12:54 p.m. UTC 
From: Stefan Markovic <smarkovic@wavecomp.com>

Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
 target/mips/helper.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Richard Henderson July 23, 2018, 4:35 p.m. UTC | #1 
On 07/19/2018 05:54 AM, Stefan Markovic wrote:
> From: Stefan Markovic <smarkovic@wavecomp.com>
> 
> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
> ---
>  target/mips/helper.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/target/mips/helper.c b/target/mips/helper.c
> index 5299f21..9535131 100644
> --- a/target/mips/helper.c
> +++ b/target/mips/helper.c
> @@ -695,6 +695,12 @@ static inline void set_badinstr_registers(CPUMIPSState *env)
>                  instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
>              }
>              env->CP0_BadInstr = instr;
> +
> +            if ((env->insn_flags & ISA_NANOMIPS32) &&
> +                ((instr & 0xFC000000) == 0x60000000)) {
> +                instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
> +                env->CP0_BadInstrX = instr;
> +            }

The nanomips condition has been checked just above.
This patch should probably be merged with 24/40.


r~
diff mbox series

Patch

diff --git a/target/mips/helper.c b/target/mips/helper.c
index 5299f21..9535131 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -695,6 +695,12 @@  static inline void set_badinstr_registers(CPUMIPSState *env)
                 instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
             }
             env->CP0_BadInstr = instr;
+
+            if ((env->insn_flags & ISA_NANOMIPS32) &&
+                ((instr & 0xFC000000) == 0x60000000)) {
+                instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
+                env->CP0_BadInstrX = instr;
+            }
         }
         if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
             (env->hflags & MIPS_HFLAG_BMASK)) {