Show patches with: Archived = No       |   435495 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v8,42/78] target/riscv: rvv-1.0: single-width bit shift instructions support vector extension v1.0 - - 1 - --- 2021-10-15 Frank Chang New
[v8,41/78] target/riscv: rvv-1.0: single-width averaging add and subtract instructions support vector extension v1.0 - - 1 - --- 2021-10-15 Frank Chang New
[v8,40/78] target/riscv: rvv-1.0: integer extension instructions support vector extension v1.0 - - 1 - --- 2021-10-15 Frank Chang New
[v8,39/78] target/riscv: rvv-1.0: whole register move instructions support vector extension v1.0 1 - - - --- 2021-10-15 Frank Chang New
[v8,38/78] target/riscv: rvv-1.0: floating-point scalar move instructions support vector extension v1.0 1 - - - --- 2021-10-15 Frank Chang New
[v8,37/78] target/riscv: rvv-1.0: floating-point move instruction support vector extension v1.0 - - 1 - --- 2021-10-15 Frank Chang New
[v8,36/78] target/riscv: rvv-1.0: integer scalar move instructions support vector extension v1.0 1 - 1 - --- 2021-10-15 Frank Chang New
[v8,35/78] target/riscv: rvv-1.0: register gather instructions support vector extension v1.0 - - 1 - --- 2021-10-15 Frank Chang New
[v8,34/78] target/riscv: rvv-1.0: allow load element with sign-extended support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,33/78] target/riscv: rvv-1.0: element index instruction support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,32/78] target/riscv: rvv-1.0: iota instruction support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,31/78] target/riscv: rvv-1.0: set-X-first mask bit instructions support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,30/78] target/riscv: rvv-1.0: find-first-set mask bit instruction support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[29/76] target/riscv: rvv-1.0: mask population count instruction support vector extension v1.0 - - 1 - --- 2021-10-15 Frank Chang New
[v8,29/78] target/riscv: rvv-1.0: count population in mask instruction Untitled series #267198 - - 2 - --- 2021-10-15 Frank Chang New
[v8,28/78] target/riscv: rvv-1.0: floating-point classify instructions support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,27/78] target/riscv: rvv-1.0: floating-point square-root instruction support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,26/78] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,25/78] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns support vector extension v1.0 - - 1 - --- 2021-10-15 Frank Chang New
[v8,24/78] target/riscv: rvv-1.0: load/store whole register instructions support vector extension v1.0 - - 1 - --- 2021-10-15 Frank Chang New
[v8,23/78] target/riscv: rvv-1.0: fault-only-first unit stride load Untitled series #267196 - - 2 - --- 2021-10-15 Frank Chang New
[23/76] target/riscv: rvv-1.0: amo operations support vector extension v1.0 - - 1 - --- 2021-10-15 Frank Chang New
[v8,22/78] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[22/76] target/riscv: rvv-1.0: fault-only-first unit stride load Untitled series #267192 - - 2 - --- 2021-10-15 Frank Chang New
[v8,21/78] target/riscv: rvv-1.0: index load and store instructions Untitled series #267193 - - 1 - --- 2021-10-15 Frank Chang New
[21/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,20/78] target/riscv: rvv-1.0: stride load and store instructions support vector extension v1.0 - - 1 - --- 2021-10-15 Frank Chang New
[20/76] target/riscv: rvv-1.0: index load and store instructions Untitled series #267190 - - 1 - --- 2021-10-15 Frank Chang New
[19/76] target/riscv: rvv-1.0: stride load and store instructions support vector extension v1.0 - - 1 - --- 2021-10-15 Frank Chang New
[v8,19/78] target/riscv: rvv-1.0: configure instructions Untitled series #267189 - - 2 - --- 2021-10-15 Frank Chang New
[v8,18/78] target/riscv: rvv-1.0: remove amo operations instructions Untitled series #267188 - - 1 - --- 2021-10-15 Frank Chang New
[18/76] target/riscv: rvv-1.0: configure instructions support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,17/78] target/riscv: rvv:1.0: add translation-time nan-box helper function support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,16/78] target/riscv: introduce more imm value modes in translator functions support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,15/78] target/riscv: rvv-1.0: update check functions support vector extension v1.0 - - 1 - --- 2021-10-15 Frank Chang New
[v8,14/78] target/riscv: rvv-1.0: add VMA and VTA support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,13/78] target/riscv: rvv-1.0: add fractional LMUL support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,12/78] target/riscv: rvv-1.0: remove MLEN calculations support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,10/78] target/riscv: rvv-1.0: add vlenb register support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,09/78] target/riscv: rvv-1.0: add vcsr register support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,07/78] target/riscv: rvv-1.0: add translation-time vector context status support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,06/78] target/riscv: rvv-1.0: introduce writable misa.v field support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,05/78] target/riscv: rvv-1.0: add sstatus VS field support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,04/78] target/riscv: rvv-1.0: add mstatus VS field support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,03/78] target/riscv: Use FIELD_EX32() to extract wd field support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,02/78] target/riscv: drop vector 0.7.1 and add 1.0 support support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v8,01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[v2,6/6] target/riscv: zfh: implement zfhmin extension target/riscv: support Zfh, Zfhmin extension v0.1 - - 1 - --- 2021-10-15 Frank Chang New
[v2,5/6] target/riscv: zfh: half-precision floating-point classify target/riscv: support Zfh, Zfhmin extension v0.1 - - 1 - --- 2021-10-15 Frank Chang New
[v2,4/6] target/riscv: zfh: half-precision floating-point compare target/riscv: support Zfh, Zfhmin extension v0.1 - - 1 - --- 2021-10-15 Frank Chang New
[v2,3/6] target/riscv: zfh: half-precision convert and move target/riscv: support Zfh, Zfhmin extension v0.1 - - 1 - --- 2021-10-15 Frank Chang New
[v2,2/6] target/riscv: zfh: half-precision computational target/riscv: support Zfh, Zfhmin extension v0.1 - - 1 - --- 2021-10-15 Frank Chang New
[v2,1/6] target/riscv: zfh: half-precision load and store target/riscv: support Zfh, Zfhmin extension v0.1 - - 1 - --- 2021-10-15 Frank Chang New
[v3,2/2] target/riscv: change the api for single/double fmin/fmax add APIs to handle alternative sNaN propagation for fmax/fmin - - - - --- 2021-10-15 Frank Chang New
[v3,1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin add APIs to handle alternative sNaN propagation for fmax/fmin - - - - --- 2021-10-15 Frank Chang New
[v3,2/2] target/riscv: change the api for single/double fmin/fmax [v3,1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin - - - - --- 2021-10-15 Frank Chang New
[v3,1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin [v3,1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin - - - - --- 2021-10-15 Frank Chang New
[v5,67/67] target/sh4: Implement prctl_unalign_sigbus user-only: Cleanup SIGSEGV and SIGBUS handling - - - - --- 2021-10-15 Richard Henderson New
[v5,66/67] target/hppa: Implement prctl_unalign_sigbus user-only: Cleanup SIGSEGV and SIGBUS handling - - - - --- 2021-10-15 Richard Henderson New
[v5,65/67] target/alpha: Implement prctl_unalign_sigbus user-only: Cleanup SIGSEGV and SIGBUS handling - - - - --- 2021-10-15 Richard Henderson New
[v5,64/67] linux-user: Add code for PR_GET/SET_UNALIGN user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,63/67] linux-user: Disable more prctl subcodes user-only: Cleanup SIGSEGV and SIGBUS handling - - - - --- 2021-10-15 Richard Henderson New
[v5,62/67] linux-user: Split out do_prctl and subroutines user-only: Cleanup SIGSEGV and SIGBUS handling - - - - --- 2021-10-15 Richard Henderson New
[v5,61/67] linux-user: Handle BUS_ADRALN in host_signal_handler user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,60/67] tcg: Add helper_unaligned_{ld, st} for user-only sigbus user-only: Cleanup SIGSEGV and SIGBUS handling - - 3 - --- 2021-10-15 Richard Henderson New
[v5,59/67] accel/tcg: Report unaligned load/store for user-only user-only: Cleanup SIGSEGV and SIGBUS handling - - 2 - --- 2021-10-15 Richard Henderson New
[v5,58/67] accel/tcg: Report unaligned atomics for user-only user-only: Cleanup SIGSEGV and SIGBUS handling - - 3 - --- 2021-10-15 Richard Henderson New
[v5,57/67] target/sparc: Set fault address in sparc_cpu_do_unaligned_access user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,56/67] target/sparc: Split out build_sfsr user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,55/67] target/sparc: Remove DEBUG_UNALIGNED user-only: Cleanup SIGSEGV and SIGBUS handling - - 2 - --- 2021-10-15 Richard Henderson New
[v5,54/67] target/sh4: Set fault address in superh_cpu_do_unaligned_access user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,53/67] linux-user/hppa: Remove POWERPC_EXCP_ALIGN handling user-only: Cleanup SIGSEGV and SIGBUS handling - - - - --- 2021-10-15 Richard Henderson New
[v5,52/67] target/s390x: Implement s390x_cpu_record_sigbus user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,51/67] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu user-only: Cleanup SIGSEGV and SIGBUS handling - - 2 - --- 2021-10-15 Richard Henderson New
[v5,50/67] target/ppc: Set fault address in ppc_cpu_do_unaligned_access user-only: Cleanup SIGSEGV and SIGBUS handling - - 2 - --- 2021-10-15 Richard Henderson New
[v5,49/67] target/ppc: Move SPR_DSISR setting to powerpc_excp user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,48/67] target/microblaze: Do not set MO_ALIGN for user-only user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,47/67] linux-user/hppa: Remove EXCP_UNALIGN handling user-only: Cleanup SIGSEGV and SIGBUS handling - - - - --- 2021-10-15 Richard Henderson New
[v5,46/67] target/arm: Implement arm_cpu_record_sigbus user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,45/67] target/alpha: Implement alpha_cpu_record_sigbus user-only: Cleanup SIGSEGV and SIGBUS handling - - - - --- 2021-10-15 Richard Henderson New
[v5,44/67] linux-user: Add cpu_loop_exit_sigbus user-only: Cleanup SIGSEGV and SIGBUS handling - - 2 - --- 2021-10-15 Richard Henderson New
[v5,43/67] hw/core: Add TCGCPUOps.record_sigbus user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,42/67] Revert "cpu: Move cpu_common_props to hw/core/cpu.c" user-only: Cleanup SIGSEGV and SIGBUS handling - - - - --- 2021-10-15 Richard Henderson New
[v5,41/67] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,40/67] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only user-only: Cleanup SIGSEGV and SIGBUS handling 1 - 1 - --- 2021-10-15 Richard Henderson New
[v5,39/67] target/sparc: Make sparc_cpu_tlb_fill sysemu only user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,38/67] target/sh4: Make sh4_cpu_tlb_fill sysemu only user-only: Cleanup SIGSEGV and SIGBUS handling - - - - --- 2021-10-15 Richard Henderson New
[v5,37/67] target/s390x: Implement s390_cpu_record_sigsegv user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,36/67] target/s390x: Use probe_access_flags in s390_probe_access user-only: Cleanup SIGSEGV and SIGBUS handling - - - - --- 2021-10-15 Richard Henderson New
[v5,35/67] target/riscv: Make riscv_cpu_tlb_fill sysemu only user-only: Cleanup SIGSEGV and SIGBUS handling - - 3 - --- 2021-10-15 Richard Henderson New
[v5,34/67] target/ppc: Implement ppc_cpu_record_sigsegv user-only: Cleanup SIGSEGV and SIGBUS handling - - 2 - --- 2021-10-15 Richard Henderson New
[v5,33/67] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,32/67] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,31/67] target/nios2: Implement nios2_cpu_record_sigsegv user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,30/67] target/mips: Make mips_cpu_tlb_fill sysemu only user-only: Cleanup SIGSEGV and SIGBUS handling - - 2 - --- 2021-10-15 Richard Henderson New
[v5,29/67] target/microblaze: Make mb_cpu_tlb_fill sysemu only user-only: Cleanup SIGSEGV and SIGBUS handling - - - - --- 2021-10-15 Richard Henderson New
[v5,28/67] target/m68k: Make m68k_cpu_tlb_fill sysemu only user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
[v5,27/67] target/i386: Implement x86_cpu_record_sigsegv user-only: Cleanup SIGSEGV and SIGBUS handling - - 1 - --- 2021-10-15 Richard Henderson New
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