Message ID | 20211015041053.2769193-59-richard.henderson@linaro.org |
---|---|
State | New |
Headers | show |
Series | user-only: Cleanup SIGSEGV and SIGBUS handling | expand |
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson < richard.henderson@linaro.org> wrote: > Use the new cpu_loop_exit_sigbus for atomic_mmu_lookup, which > has access to complete alignment info from the TCGMemOpIdx arg. > > Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > accel/tcg/user-exec.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > Reviewed-by: Warner Losh <imp@bsdimp.com> > diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c > index 5646f8e527..92cbffd7c6 100644 > --- a/accel/tcg/user-exec.c > +++ b/accel/tcg/user-exec.c > @@ -476,11 +476,22 @@ static void *atomic_mmu_lookup(CPUArchState *env, > target_ulong addr, > MemOpIdx oi, int size, int prot, > uintptr_t retaddr) > { > + MemOp mop = get_memop(oi); > + int a_bits = get_alignment_bits(mop); > + void *ret; > + > + /* Enforce guest required alignment. */ > + if (unlikely(addr & ((1 << a_bits) - 1))) { > + MMUAccessType t = prot == PAGE_READ ? MMU_DATA_LOAD : > MMU_DATA_STORE; > + cpu_loop_exit_sigbus(env_cpu(env), addr, t, retaddr); > + } > + > /* Enforce qemu required alignment. */ > if (unlikely(addr & (size - 1))) { > cpu_loop_exit_atomic(env_cpu(env), retaddr); > } > - void *ret = g2h(env_cpu(env), addr); > + > + ret = g2h(env_cpu(env), addr); > set_helper_retaddr(retaddr); > return ret; > } > -- > 2.25.1 > >
On 10/15/21 06:10, Richard Henderson wrote: > Use the new cpu_loop_exit_sigbus for atomic_mmu_lookup, which > has access to complete alignment info from the TCGMemOpIdx arg. > > Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > accel/tcg/user-exec.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c > index 5646f8e527..92cbffd7c6 100644 > --- a/accel/tcg/user-exec.c > +++ b/accel/tcg/user-exec.c > @@ -476,11 +476,22 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, > MemOpIdx oi, int size, int prot, > uintptr_t retaddr) > { > + MemOp mop = get_memop(oi); > + int a_bits = get_alignment_bits(mop); > + void *ret; > + > + /* Enforce guest required alignment. */ > + if (unlikely(addr & ((1 << a_bits) - 1))) { QEMU_IS_ALIGNED(addr, 1 << a_bits) ? > + MMUAccessType t = prot == PAGE_READ ? MMU_DATA_LOAD : MMU_DATA_STORE; > + cpu_loop_exit_sigbus(env_cpu(env), addr, t, retaddr); > + } Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5646f8e527..92cbffd7c6 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -476,11 +476,22 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, int size, int prot, uintptr_t retaddr) { + MemOp mop = get_memop(oi); + int a_bits = get_alignment_bits(mop); + void *ret; + + /* Enforce guest required alignment. */ + if (unlikely(addr & ((1 << a_bits) - 1))) { + MMUAccessType t = prot == PAGE_READ ? MMU_DATA_LOAD : MMU_DATA_STORE; + cpu_loop_exit_sigbus(env_cpu(env), addr, t, retaddr); + } + /* Enforce qemu required alignment. */ if (unlikely(addr & (size - 1))) { cpu_loop_exit_atomic(env_cpu(env), retaddr); } - void *ret = g2h(env_cpu(env), addr); + + ret = g2h(env_cpu(env), addr); set_helper_retaddr(retaddr); return ret; }