| Message ID | 20211015074627.3957162-47-frank.chang@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | support vector extension v1.0 | expand |
On Fri, Oct 15, 2021 at 6:18 PM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > Add the following instructions: > > * vmv1r.v > * vmv2r.v > * vmv4r.v > * vmv8r.v > > Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn32.decode | 4 ++++ > target/riscv/insn_trans/trans_rvv.c.inc | 25 +++++++++++++++++++++++++ > 2 files changed, 29 insertions(+) > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index ab5fdbf9be8..06a80763112 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -650,6 +650,10 @@ vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm > vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm > vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm > vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r > +vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd > +vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd > +vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd > +vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd > > vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm > vsetvl 1000000 ..... ..... 111 ..... 1010111 @r > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index aec0316fba4..5eaf978fe90 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -3258,3 +3258,28 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a) > } > return false; > } > + > +/* > + * Whole Vector Register Move Instructions ignore vtype and vl setting. > + * Thus, we don't need to check vill bit. (Section 16.6) > + */ > +#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \ > +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ > +{ \ > + if (require_rvv(s) && \ > + QEMU_IS_ALIGNED(a->rd, LEN) && \ > + QEMU_IS_ALIGNED(a->rs2, LEN)) { \ > + /* EEW = 8 */ \ > + tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \ > + vreg_ofs(s, a->rs2), \ > + s->vlen / 8 * LEN, s->vlen / 8 * LEN); \ > + mark_vs_dirty(s); \ > + return true; \ > + } \ > + return false; \ > +} > + > +GEN_VMV_WHOLE_TRANS(vmv1r_v, 1) > +GEN_VMV_WHOLE_TRANS(vmv2r_v, 2) > +GEN_VMV_WHOLE_TRANS(vmv4r_v, 4) > +GEN_VMV_WHOLE_TRANS(vmv8r_v, 8) > -- > 2.25.1 > >
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index ab5fdbf9be8..06a80763112 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -650,6 +650,10 @@ vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r +vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd +vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd +vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd +vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index aec0316fba4..5eaf978fe90 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3258,3 +3258,28 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a) } return false; } + +/* + * Whole Vector Register Move Instructions ignore vtype and vl setting. + * Thus, we don't need to check vill bit. (Section 16.6) + */ +#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \ +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ +{ \ + if (require_rvv(s) && \ + QEMU_IS_ALIGNED(a->rd, LEN) && \ + QEMU_IS_ALIGNED(a->rs2, LEN)) { \ + /* EEW = 8 */ \ + tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \ + vreg_ofs(s, a->rs2), \ + s->vlen / 8 * LEN, s->vlen / 8 * LEN); \ + mark_vs_dirty(s); \ + return true; \ + } \ + return false; \ +} + +GEN_VMV_WHOLE_TRANS(vmv1r_v, 1) +GEN_VMV_WHOLE_TRANS(vmv2r_v, 2) +GEN_VMV_WHOLE_TRANS(vmv4r_v, 4) +GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)