| Message ID | 20200529111322.7184-27-miquel.raynal@bootlin.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | Allow vendor drivers to propose their own timings | expand |
On Fri, 29 May 2020 13:13:20 +0200 Miquel Raynal <miquel.raynal@bootlin.com> wrote: > From: Rickard x Andersson <rickaran@axis.com> > > The Kioxia/Toshiba TH58NVG2S3HBAI4 NAND memory is not ONFI compliant. > The timings of the NAND chip memory are quite close to ONFI mode 4 but > is breaking that spec. > > By providing our own set of timings, erase block read speed is increased > from 6910 kiB/s to 13490 kiB/s and erase block write speed is increased > from 3350 kiB/s to 4410 kiB/s. > > Tested on IMX6SX which has a NAND controller supporting EDO mode. > > Signed-off-by: Rickard x Andersson <rickaran@axis.com> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> > --- > drivers/mtd/nand/raw/nand_ids.c | 3 +++ > drivers/mtd/nand/raw/nand_toshiba.c | 38 +++++++++++++++++++++++++++++ > 2 files changed, 41 insertions(+) > > diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c > index 3b890d55703d..b9945791a9d7 100644 > --- a/drivers/mtd/nand/raw/nand_ids.c > +++ b/drivers/mtd/nand/raw/nand_ids.c > @@ -51,6 +51,9 @@ struct nand_flash_dev nand_flash_ids[] = { > { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, > SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, > NAND_ECC_INFO(40, SZ_1K) }, > + {"TH58NVG2S3HBAI4 4G 3.3V 8-bit", > + { .id = {0x98, 0xdc, 0x91, 0x15, 0x76} }, > + SZ_2K, SZ_512, SZ_128K, 0, 5, 128, NAND_ECC_INFO(8, SZ_512) }, > > LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), > LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), > diff --git a/drivers/mtd/nand/raw/nand_toshiba.c b/drivers/mtd/nand/raw/nand_toshiba.c > index 6d53f9b7a817..f746c19f3b2c 100644 > --- a/drivers/mtd/nand/raw/nand_toshiba.c > +++ b/drivers/mtd/nand/raw/nand_toshiba.c > @@ -212,6 +212,33 @@ tc58nvg0s3e_choose_interface_config(struct nand_chip *chip, > return nand_choose_best_sdr_timings(chip, iface, NULL); > } > > +static int > +th58nvg2s3hbai4_choose_interface_config(struct nand_chip *chip, > + struct nand_interface_config *iface) > +{ > + struct nand_sdr_timings *sdr = &iface->timings.sdr; > + > + /* Start with timings from the closest timing mode, mode 4. */ > + onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 4); > + > + /* Patch timings that differ from mode 4. */ > + sdr->tALS_min = 12000; > + sdr->tCHZ_max = 20000; > + sdr->tCLS_min = 12000; > + sdr->tCOH_min = 0; > + sdr->tDS_min = 12000; > + sdr->tRHOH_min = 25000; > + sdr->tRHW_min = 30000; > + sdr->tRHZ_max = 60000; > + sdr->tWHR_min = 60000; > + > + /* Patch timings not part of onfi timing mode. */ > + sdr->tPROG_max = 700000000; > + sdr->tBERS_max = 5000000000; > + > + return nand_choose_best_sdr_timings(chip, iface, sdr); > +} > + > static int tc58teg5dclta00_init(struct nand_chip *chip) > { > struct mtd_info *mtd = nand_to_mtd(chip); > @@ -232,6 +259,14 @@ static int tc58nvg0s3e_init(struct nand_chip *chip) > return 0; > } > > +static int th58nvg2s3hbai4_init(struct nand_chip *chip) > +{ > + chip->ops.choose_interface_config = > + &th58nvg2s3hbai4_choose_interface_config; > + > + return 0; > +} > + > static int toshiba_nand_init(struct nand_chip *chip) > { > if (nand_is_slc(chip)) > @@ -247,6 +282,9 @@ static int toshiba_nand_init(struct nand_chip *chip) > if (!strncmp("TC58NVG0S3E", chip->parameters.model, > sizeof("TC58NVG0S3E") - 1)) > tc58nvg0s3e_init(chip); > + if (!strncmp("TH58NVG2S3HBAI4", chip->parameters.model, > + sizeof("TH58NVG2S3HBAI4") - 1)) > + th58nvg2s3hbai4_init(chip); > > return 0; > }
On Fri, 2020-05-29 at 11:13:20 UTC, Miquel Raynal wrote: > From: Rickard x Andersson <rickaran@axis.com> > > The Kioxia/Toshiba TH58NVG2S3HBAI4 NAND memory is not ONFI compliant. > The timings of the NAND chip memory are quite close to ONFI mode 4 but > is breaking that spec. > > By providing our own set of timings, erase block read speed is increased > from 6910 kiB/s to 13490 kiB/s and erase block write speed is increased > from 3350 kiB/s to 4410 kiB/s. > > Tested on IMX6SX which has a NAND controller supporting EDO mode. > > Signed-off-by: Rickard x Andersson <rickaran@axis.com> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next. Miquel
diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index 3b890d55703d..b9945791a9d7 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -51,6 +51,9 @@ struct nand_flash_dev nand_flash_ids[] = { { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, NAND_ECC_INFO(40, SZ_1K) }, + {"TH58NVG2S3HBAI4 4G 3.3V 8-bit", + { .id = {0x98, 0xdc, 0x91, 0x15, 0x76} }, + SZ_2K, SZ_512, SZ_128K, 0, 5, 128, NAND_ECC_INFO(8, SZ_512) }, LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), diff --git a/drivers/mtd/nand/raw/nand_toshiba.c b/drivers/mtd/nand/raw/nand_toshiba.c index 6d53f9b7a817..f746c19f3b2c 100644 --- a/drivers/mtd/nand/raw/nand_toshiba.c +++ b/drivers/mtd/nand/raw/nand_toshiba.c @@ -212,6 +212,33 @@ tc58nvg0s3e_choose_interface_config(struct nand_chip *chip, return nand_choose_best_sdr_timings(chip, iface, NULL); } +static int +th58nvg2s3hbai4_choose_interface_config(struct nand_chip *chip, + struct nand_interface_config *iface) +{ + struct nand_sdr_timings *sdr = &iface->timings.sdr; + + /* Start with timings from the closest timing mode, mode 4. */ + onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 4); + + /* Patch timings that differ from mode 4. */ + sdr->tALS_min = 12000; + sdr->tCHZ_max = 20000; + sdr->tCLS_min = 12000; + sdr->tCOH_min = 0; + sdr->tDS_min = 12000; + sdr->tRHOH_min = 25000; + sdr->tRHW_min = 30000; + sdr->tRHZ_max = 60000; + sdr->tWHR_min = 60000; + + /* Patch timings not part of onfi timing mode. */ + sdr->tPROG_max = 700000000; + sdr->tBERS_max = 5000000000; + + return nand_choose_best_sdr_timings(chip, iface, sdr); +} + static int tc58teg5dclta00_init(struct nand_chip *chip) { struct mtd_info *mtd = nand_to_mtd(chip); @@ -232,6 +259,14 @@ static int tc58nvg0s3e_init(struct nand_chip *chip) return 0; } +static int th58nvg2s3hbai4_init(struct nand_chip *chip) +{ + chip->ops.choose_interface_config = + &th58nvg2s3hbai4_choose_interface_config; + + return 0; +} + static int toshiba_nand_init(struct nand_chip *chip) { if (nand_is_slc(chip)) @@ -247,6 +282,9 @@ static int toshiba_nand_init(struct nand_chip *chip) if (!strncmp("TC58NVG0S3E", chip->parameters.model, sizeof("TC58NVG0S3E") - 1)) tc58nvg0s3e_init(chip); + if (!strncmp("TH58NVG2S3HBAI4", chip->parameters.model, + sizeof("TH58NVG2S3HBAI4") - 1)) + th58nvg2s3hbai4_init(chip); return 0; }