@@ -130,7 +130,7 @@ static inline int nand_exec_op(struct nand_chip *chip,
return chip->controller->ops->exec_op(chip, op, false);
}
-static inline bool nand_has_setup_data_iface(struct nand_chip *chip)
+static inline bool nand_controller_can_setup_data_iface(struct nand_chip *chip)
{
if (!chip->controller || !chip->controller->ops ||
!chip->controller->ops->setup_data_interface)
@@ -910,7 +910,7 @@ static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
{
int ret;
- if (!nand_has_setup_data_iface(chip))
+ if (!nand_controller_can_setup_data_iface(chip))
return 0;
/*
@@ -955,7 +955,7 @@ static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { mode, };
int ret;
- if (!nand_has_setup_data_iface(chip))
+ if (!nand_controller_can_setup_data_iface(chip))
return 0;
/* Change the mode on the chip side (if supported by the NAND chip) */
@@ -1025,7 +1025,7 @@ static int nand_init_data_interface(struct nand_chip *chip)
{
int modes, mode, ret;
- if (!nand_has_setup_data_iface(chip))
+ if (!nand_controller_can_setup_data_iface(chip))
return 0;
/*
@@ -365,7 +365,7 @@ static void nand_ccs_delay(struct nand_chip *chip)
* Wait tCCS_min if it is correctly defined, otherwise wait 500ns
* (which should be safe for all NANDs).
*/
- if (nand_has_setup_data_iface(chip))
+ if (nand_controller_can_setup_data_iface(chip))
ndelay(chip->data_interface.timings.sdr.tCCS_min / 1000);
else
ndelay(500);