Show patches with: Archived = No       |   127397 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
RISC-V: Refactor and cleanup fma patterns RISC-V: Refactor and cleanup fma patterns - - - - --- 2023-09-18 Lehua Ding New
RISC-V: Refactor and cleanup vsetvl pass RISC-V: Refactor and cleanup vsetvl pass - - - - --- 2023-10-16 Lehua Ding New
RISC-V: Refactor expand_reduction and cleanup enum reduction_type RISC-V: Refactor expand_reduction and cleanup enum reduction_type - - - - --- 2023-09-15 Lehua Ding New
RISC-V: Refactor requirement of ZVFH and ZVFHMIN. RISC-V: Refactor requirement of ZVFH and ZVFHMIN. - - - - --- 2023-06-07 Li, Pan2 via Gcc-patches New
RISC-V: Refactor the framework of RVV auto-vectorization RISC-V: Refactor the framework of RVV auto-vectorization - - - - --- 2023-05-23 juzhe.zhong@rivai.ai New
RISC-V: Refactor the integer ternary autovec pattern RISC-V: Refactor the integer ternary autovec pattern - - - - --- 2023-06-21 juzhe.zhong@rivai.ai New
RISC-V: Refactor the or pattern to switch cases RISC-V: Refactor the or pattern to switch cases - - - - --- 2023-05-14 Li, Pan2 via Gcc-patches New
RISC-V: Refine Phase 3 of VSETVL PASS RISC-V: Refine Phase 3 of VSETVL PASS - - - - --- 2023-01-04 juzhe.zhong@rivai.ai New
RISC-V: Refine codes in backward fusion RISC-V: Refine codes in backward fusion - - - - --- 2023-01-09 juzhe.zhong@rivai.ai New
RISC-V: Refine function args of some functions. RISC-V: Refine function args of some functions. - - - - --- 2023-01-18 juzhe.zhong@rivai.ai New
RISC-V: Refine reduction RA constraint according to RVV ISA RISC-V: Refine reduction RA constraint according to RVV ISA - - - - --- 2023-03-13 juzhe.zhong@rivai.ai New
RISC-V: Refine register_builtin_types function. RISC-V: Refine register_builtin_types function. - - - - --- 2022-10-11 juzhe.zhong@rivai.ai New
RISC-V: Refine riscv-vector-builtins.o include files and makefile. RISC-V: Refine riscv-vector-builtins.o include files and makefile. - - - - --- 2022-10-11 juzhe.zhong@rivai.ai New
RISC-V: Refine the condition for add additional vars in RVV cost model RISC-V: Refine the condition for add additional vars in RVV cost model - - - - --- 2024-03-28 Demin Han New
RISC-V: Refine unsigned avg_floor/avg_ceil RISC-V: Refine unsigned avg_floor/avg_ceil - - - - --- 2024-01-10 juzhe.zhong@rivai.ai New
RISC-V: Remove "extern“ for namespace [NFC] RISC-V: Remove "extern“ for namespace [NFC] - - - - --- 2023-02-14 juzhe.zhong@rivai.ai New
RISC-V: Remove @ of vec_series RISC-V: Remove @ of vec_series - - - - --- 2023-10-04 juzhe.zhong@rivai.ai New
RISC-V: Remove DCE in VSETVL PASS RISC-V: Remove DCE in VSETVL PASS - - - - --- 2023-01-18 juzhe.zhong@rivai.ai New
RISC-V: Remove FRM for vfncvt.rod instruction RISC-V: Remove FRM for vfncvt.rod instruction - - - - --- 2023-05-31 juzhe.zhong@rivai.ai New
RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion) RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion) - - - - --- 2023-05-31 juzhe.zhong@rivai.ai New
RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening conversion) RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening conversion) - - - - --- 2023-05-31 juzhe.zhong@rivai.ai New
RISC-V: Remove FRM_REGNUM dependency for rtx conversions RISC-V: Remove FRM_REGNUM dependency for rtx conversions - - - - --- 2023-05-24 juzhe.zhong@rivai.ai New
RISC-V: Remove TUPLE size macro define. RISC-V: Remove TUPLE size macro define. - - - - --- 2022-10-11 juzhe.zhong@rivai.ai New
RISC-V: Remove XFAIL of ssa-dom-cse-2.c RISC-V: Remove XFAIL of ssa-dom-cse-2.c - - - - --- 2023-10-11 juzhe.zhong@rivai.ai New
RISC-V: Remove autovec-vls.md file and clean up VLS move modes[NFC] RISC-V: Remove autovec-vls.md file and clean up VLS move modes[NFC] - - - - --- 2023-09-18 juzhe.zhong@rivai.ai New
RISC-V: Remove dirty_pat since it is redundant RISC-V: Remove dirty_pat since it is redundant - - - - --- 2023-01-09 juzhe.zhong@rivai.ai New
RISC-V: Remove duplicate `#include "riscv-vector-switch.def"` RISC-V: Remove duplicate `#include "riscv-vector-switch.def"` - - - - --- 2023-06-13 Lehua Ding New
RISC-V: Remove duplicate `order_operator' predicate RISC-V: Remove duplicate `order_operator' predicate - - - - --- 2023-11-19 Maciej W. Rozycki New
RISC-V: Remove duplicate backslashes from `stack_protect_set_<mode>' RISC-V: Remove duplicate backslashes from `stack_protect_set_<mode>' - - - - --- 2022-07-26 Maciej W. Rozycki New
RISC-V: Remove earlyclobber for wx/wf instructions. RISC-V: Remove earlyclobber for wx/wf instructions. - - - - --- 2023-11-30 juzhe.zhong@rivai.ai New
RISC-V: Remove earlyclobber from widen reduction RISC-V: Remove earlyclobber from widen reduction - - - - --- 2023-12-04 juzhe.zhong@rivai.ai New
RISC-V: Remove incorrect earliest vsetvl post optimization[PR111313] RISC-V: Remove incorrect earliest vsetvl post optimization[PR111313] - - - - --- 2023-09-07 juzhe.zhong@rivai.ai New
RISC-V: Remove incorrect function gate gather_scatter_valid_offset_mode_p RISC-V: Remove incorrect function gate gather_scatter_valid_offset_mode_p - - - - --- 2023-11-25 juzhe.zhong@rivai.ai New
RISC-V: Remove masking third operand of rotate instructions RISC-V: Remove masking third operand of rotate instructions - - - - --- 2023-05-10 Jivan Hakobyan New
RISC-V: Remove math.h import to resolve missing stubs failures RISC-V: Remove math.h import to resolve missing stubs failures - - - 2 --- 2023-09-20 Patrick O'Neill New
RISC-V: Remove movmisalign pattern for VLA modes RISC-V: Remove movmisalign pattern for VLA modes - - - - --- 2023-08-29 juzhe.zhong@rivai.ai New
RISC-V: Remove non-existing 'Zve32d' extension RISC-V: Remove non-existing 'Zve32d' extension - - - - --- 2023-08-09 Tsukasa OI New
RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412] RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412] - - - - --- 2023-09-18 Li Xu New
RISC-V: Remove poly selftest when --preference=fixed-vlmax RISC-V: Remove poly selftest when --preference=fixed-vlmax - - - - --- 2023-12-11 juzhe.zhong@rivai.ai New
RISC-V: Remove redundant attributes RISC-V: Remove redundant attributes - - - - --- 2023-01-27 juzhe.zhong@rivai.ai New
RISC-V: Remove redundant functions RISC-V: Remove redundant functions - - - - --- 2023-09-11 juzhe.zhong@rivai.ai New
RISC-V: Remove redundant printf of abs-run.c RISC-V: Remove redundant printf of abs-run.c - - - - --- 2023-05-29 juzhe.zhong@rivai.ai New
RISC-V: Remove redundant vcond patterns RISC-V: Remove redundant vcond patterns - - - - --- 2023-06-26 juzhe.zhong@rivai.ai New
RISC-V: Remove redundant vec_duplicate pattern RISC-V: Remove redundant vec_duplicate pattern - - - - --- 2023-09-18 juzhe.zhong@rivai.ai New
RISC-V: Remove redundant vlmul_ext_* patterns to fix PR110109 RISC-V: Remove redundant vlmul_ext_* patterns to fix PR110109 - - - - --- 2023-06-04 juzhe.zhong@rivai.ai New
RISC-V: Remove side effects of vsetvl pattern in RTL. RISC-V: Remove side effects of vsetvl pattern in RTL. - - - - --- 2022-12-20 juzhe.zhong@rivai.ai New
RISC-V: Remove side effects of vsetvl/vsetvlmax intriniscs in properties RISC-V: Remove side effects of vsetvl/vsetvlmax intriniscs in properties - - - - --- 2022-12-20 juzhe.zhong@rivai.ai New
RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst - - - - --- 2022-11-29 juzhe.zhong@rivai.ai New
RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst - - - - --- 2022-11-28 juzhe.zhong@rivai.ai New
RISC-V: Remove testcase that cannot be compiled because VLEN limitation RISC-V: Remove testcase that cannot be compiled because VLEN limitation - - - - --- 2023-07-18 Lehua Ding New
RISC-V: Remove the redundant expressions in the and<mode>3. RISC-V: Remove the redundant expressions in the and<mode>3. - - - - --- 2023-07-14 Die Li New
RISC-V: Remove trailing spaces on lines. RISC-V: Remove trailing spaces on lines. - - - - --- 2023-05-17 Jin Ma New
RISC-V: Remove unit-stride store from ta attribute RISC-V: Remove unit-stride store from ta attribute - - - - --- 2022-12-14 juzhe.zhong@rivai.ai New
RISC-V: Remove unnecessary md pattern for TARGET_XTHEADCONDMOV RISC-V: Remove unnecessary md pattern for TARGET_XTHEADCONDMOV - - - - --- 2023-06-02 Die Li New
RISC-V: Remove unnecessary register class. RISC-V: Remove unnecessary register class. - - - - --- 2023-02-03 Monk Chiang New
RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit - - - - --- 2023-09-06 juzhe.zhong@rivai.ai New
RISC-V: Remove unused TI/TF vector modes. RISC-V: Remove unused TI/TF vector modes. - - - - --- 2022-10-24 juzhe.zhong@rivai.ai New
RISC-V: Remove unused redundant vector attributes RISC-V: Remove unused redundant vector attributes - - - - --- 2022-12-14 juzhe.zhong@rivai.ai New
RISC-V: Remove useless modes RISC-V: Remove useless modes - - - - --- 2023-12-06 Li Xu New
RISC-V: Remove void_type_node of void_args for vsetvlmax intrinsic RISC-V: Remove void_type_node of void_args for vsetvlmax intrinsic - - - - --- 2023-02-27 juzhe.zhong@rivai.ai New
RISC-V: Remove vsetvl_pre bogus instructions in VSETVL PASS RISC-V: Remove vsetvl_pre bogus instructions in VSETVL PASS - - - - --- 2024-02-01 juzhe.zhong@rivai.ai New
RISC-V: Remove vxrm parameter for vsadd[u] and vssub[u] RISC-V: Remove vxrm parameter for vsadd[u] and vssub[u] - - - - --- 2023-07-28 Li Xu New
RISC-V: Remove xfail from ssa-fre-3.c testcase RISC-V: Remove xfail from ssa-fre-3.c testcase - - 1 - --- 2023-12-06 Edwin Lu New
RISC-V: Removed misleading comments in testcases RISC-V: Removed misleading comments in testcases - - - - --- 2023-09-18 Lehua Ding New
RISC-V: Removed unnecessary sign-extend for vsetvl RISC-V: Removed unnecessary sign-extend for vsetvl - - - - --- 2023-11-08 Lehua Ding New
RISC-V: Rename and unify stringop strategy handling [NFC]. RISC-V: Rename and unify stringop strategy handling [NFC]. - - - - --- 2023-12-01 Robin Dapp New
RISC-V: Rename insn into rinsn for rtx_insn * RISC-V: Rename insn into rinsn for rtx_insn * - - - - --- 2023-01-09 juzhe.zhong@rivai.ai New
RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names - - - - --- 2023-09-21 Lehua Ding New
RISC-V: Rename some variables of vector_block_info[NFC] RISC-V: Rename some variables of vector_block_info[NFC] - - - - --- 2023-10-20 juzhe.zhong@rivai.ai New
RISC-V: Rename tu_preds to none_tu_preds [NFC] RISC-V: Rename tu_preds to none_tu_preds [NFC] - - - - --- 2023-02-15 juzhe.zhong@rivai.ai New
RISC-V: Reorder VSETVL PASS location RISC-V: Reorder VSETVL PASS location - - - - --- 2023-01-18 juzhe.zhong@rivai.ai New
RISC-V: Reorganize and rename combine patterns in autovec-opt.md RISC-V: Reorganize and rename combine patterns in autovec-opt.md - - - - --- 2023-09-20 Lehua Ding New
RISC-V: Reorganize binary autovec testcases RISC-V: Reorganize binary autovec testcases - - - - --- 2023-05-12 juzhe.zhong@rivai.ai New
RISC-V: Reorganize mangle_builtin_type.[NFC] RISC-V: Reorganize mangle_builtin_type.[NFC] - - - - --- 2022-10-14 juzhe.zhong@rivai.ai New
RISC-V: Reorganize the code of CONST_VECTOR handling in riscv.cc RISC-V: Reorganize the code of CONST_VECTOR handling in riscv.cc - - - - --- 2023-05-22 juzhe.zhong@rivai.ai New
RISC-V: Replace CONSTEXPR with constexpr RISC-V: Replace CONSTEXPR with constexpr - - - - --- 2022-10-24 juzhe.zhong@rivai.ai New
RISC-V: Replace not + bitwise_imm with li + bitwise_not RISC-V: Replace not + bitwise_imm with li + bitwise_not - - - - --- 2023-09-11 Jivan Hakobyan New
RISC-V: Replace rtx REG for zero REGS operations RISC-V: Replace rtx REG for zero REGS operations - - - - --- 2023-09-07 juzhe.zhong@rivai.ai New
RISC-V: Replace simm32_p with immediate_operand (Pmode) RISC-V: Replace simm32_p with immediate_operand (Pmode) - - - - --- 2023-02-14 juzhe.zhong@rivai.ai New
RISC-V: Replace unspec with bitreverse in riscv_brev8_<mode> insn RISC-V: Replace unspec with bitreverse in riscv_brev8_<mode> insn - - - - --- 2023-07-26 Jivan Hakobyan New
RISC-V: Report Sorry when users enable RVV in big-endian mode [PR113404] RISC-V: Report Sorry when users enable RVV in big-endian mode [PR113404] - - - - --- 2024-01-16 juzhe.zhong@rivai.ai New
RISC-V: Require a extension for ztso testcases with atomic insns RISC-V: Require a extension for ztso testcases with atomic insns 1 - 1 - --- 2024-03-21 Patrick O'Neill New
RISC-V: Reset the length to the default of 4 for FP comparisons RISC-V: Reset the length to the default of 4 for FP comparisons - - - - --- 2022-06-09 Maciej W. Rozycki New
RISC-V: Return const ref. for vl_vtype_info::get_avl_info RISC-V: Return const ref. for vl_vtype_info::get_avl_info - - - - --- 2022-12-27 Kito Cheng New
RISC-V: Return machine_mode rather than opt_machine_mode for get_mask_mode, NFC RISC-V: Return machine_mode rather than opt_machine_mode for get_mask_mode, NFC - - - - --- 2023-07-31 Kito Cheng New
RISC-V: Revert the convert from vmv.s.x to vmv.v.i RISC-V: Revert the convert from vmv.s.x to vmv.v.i - - - - --- 2024-02-20 Alexandre Oliva New
RISC-V: Revert the convert from vmv.s.x to vmv.v.i RISC-V: Revert the convert from vmv.s.x to vmv.v.i - - - - --- 2023-08-11 Lehua Ding New
RISC-V: Revert this weekend's changes RISC-V: Revert this weekend's changes - 18 - - --- 2024-04-22 Palmer Dabbelt New
RISC-V: Revive test case PR 102957 RISC-V: Revive test case PR 102957 - - - - --- 2023-08-11 Tsukasa OI New
RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS - - - - --- 2023-06-09 juzhe.zhong@rivai.ai New
RISC-V: Robostify shuffle index used by vrgather and fix regression RISC-V: Robostify shuffle index used by vrgather and fix regression - - - - --- 2023-12-11 juzhe.zhong@rivai.ai New
RISC-V: Robustify vec_init pattern[NFC] RISC-V: Robustify vec_init pattern[NFC] - - - - --- 2023-11-10 juzhe.zhong@rivai.ai New
RISC-V: Save and restore FCSR in interrupt functions to avoid program errors. RISC-V: Save and restore FCSR in interrupt functions to avoid program errors. - - - - --- 2023-06-13 Jin Ma New
RISC-V: Save/restore ra register correctly [PR112478] RISC-V: Save/restore ra register correctly [PR112478] - - 1 1 --- 2023-11-14 Kito Cheng New
RISC-V: Set SLOW_BYTE_ACCESS=1 RISC-V: Set SLOW_BYTE_ACCESS=1 - - - - --- 2017-11-03 Palmer Dabbelt New
RISC-V: Set require-effective-target rv64 for PR113742 RISC-V: Set require-effective-target rv64 for PR113742 - - - - --- 2024-02-14 Edwin Lu New
RISC-V: Set the ABI for the RVV tests RISC-V: Set the ABI for the RVV tests - - - - --- 2023-04-13 Palmer Dabbelt New
RISC-V: Set the natural size of constant vector mask modes to one RVV data vector. RISC-V: Set the natural size of constant vector mask modes to one RVV data vector. - - - - --- 2023-06-20 Li Xu New
RISC-V: Short-forward-branch opt for SiFive 7 series cores. RISC-V: Short-forward-branch opt for SiFive 7 series cores. - - - - --- 2019-04-30 Jim Wilson New
RISC-V: Shorten memrefs improvement, partial fix 97417. RISC-V: Shorten memrefs improvement, partial fix 97417. - - - - --- 2021-02-13 Jim Wilson New
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