Show patches with: State = Action Required       |   126954 patches
« 1 2 ... 366 367 368 … 1269 1270 »
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
RISC-V: bitmanip: use bexti for "(a & (1 << BIT_NO)) ? 0 : -1" RISC-V: bitmanip: use bexti for "(a & (1 << BIT_NO)) ? 0 : -1" - - - - --- 2022-11-08 Philipp Tomsich New
RISC-V: split to allow formation of sh[123]add before divw RISC-V: split to allow formation of sh[123]add before divw - - - - --- 2022-11-08 Philipp Tomsich New
RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w - - - - --- 2022-11-08 Philipp Tomsich New
RISC-V: allow bseti on SImode without sign-extension RISC-V: allow bseti on SImode without sign-extension - - - - --- 2022-11-08 Philipp Tomsich New
RISC-V: Optimize branches testing a bit-range or a shifted immediate RISC-V: Optimize branches testing a bit-range or a shifted immediate - - - - --- 2022-11-08 Philipp Tomsich New
RISC-V: No extensions for SImode min/max against safe constant RISC-V: No extensions for SImode min/max against safe constant - - - - --- 2022-11-08 Philipp Tomsich New
[v2] RISC-V: No extensions for SImode min/max against safe constant [v2] RISC-V: No extensions for SImode min/max against safe constant - - - - --- 2022-11-09 Philipp Tomsich New
RISC-V: Optimise adding a (larger than simm12) constant RISC-V: Optimise adding a (larger than simm12) constant - - - - --- 2022-11-09 Philipp Tomsich New
RISC-V: Implement movmisalign<mode> to enable SLP RISC-V: Implement movmisalign<mode> to enable SLP - - - - --- 2022-11-09 Philipp Tomsich New
ifcombine: recognize single bit test of sign-bit ifcombine: recognize single bit test of sign-bit - - - - --- 2022-11-09 Philipp Tomsich New
ifcombine: fold two bit tests with different polarity ifcombine: fold two bit tests with different polarity - - - - --- 2022-11-09 Philipp Tomsich New
[v2,WIP] RISC-V: Replace zero_extendsidi2_shifted with generalized split [v2,WIP] RISC-V: Replace zero_extendsidi2_shifted with generalized split - - - - --- 2022-11-09 Philipp Tomsich New
[v3] RISC-V: Replace zero_extendsidi2_shifted with generalized split [v3] RISC-V: Replace zero_extendsidi2_shifted with generalized split - - - - --- 2022-11-09 Philipp Tomsich New
RISC-V: Fix selection of pipeline model for sifive-7-series RISC-V: Fix selection of pipeline model for sifive-7-series - - - - --- 2022-11-09 Philipp Tomsich New
[v2] RISC-V: costs: support shift-and-add in strength-reduction [v2] RISC-V: costs: support shift-and-add in strength-reduction - - - - --- 2022-11-10 Philipp Tomsich New
RISC-V: Use bseti to cover more immediates than with ori alone RISC-V: Use bseti to cover more immediates than with ori alone - - - - --- 2022-11-10 Philipp Tomsich New
RISC-V: Use binvi to cover more immediates than with xori alone RISC-V: Use binvi to cover more immediates than with xori alone - - - - --- 2022-11-10 Philipp Tomsich New
RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND - - - - --- 2022-11-10 Philipp Tomsich New
[1/7] RISC-V: Recognize xventanacondops extension RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - - --- 2022-11-12 Philipp Tomsich New
[2/7] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - - --- 2022-11-12 Philipp Tomsich New
[3/7] RISC-V: Support noce_try_store_flag_mask as vt.maskc<n> RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - - --- 2022-11-12 Philipp Tomsich New
[4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - - --- 2022-11-12 Philipp Tomsich New
[5/7] RISC-V: Recognize bexti in negated if-conversion RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - - --- 2022-11-12 Philipp Tomsich New
[6/7] RISC-V: Support immediates in XVentanaCondOps RISC-V: Backend support for XVentanaCondOps/ZiCondops - - 1 - --- 2022-11-12 Philipp Tomsich New
[7/7] ifcvt: add if-conversion to conditional-zero instructions RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - - --- 2022-11-12 Philipp Tomsich New
doc: Update Jeff Law's email-address in contrib.rst doc: Update Jeff Law's email-address in contrib.rst - - - - --- 2022-11-13 Philipp Tomsich New
aarch64: Add support for Ampere-1A (-mcpu=ampere1a) CPU aarch64: Add support for Ampere-1A (-mcpu=ampere1a) CPU - - - - --- 2022-11-13 Philipp Tomsich New
RISC-V: Use .p2align for code-alignment RISC-V: Use .p2align for code-alignment - - - - --- 2022-11-13 Philipp Tomsich New
RISC-V: Zihintpause: add __builtin_riscv_pause RISC-V: Zihintpause: add __builtin_riscv_pause - - - - --- 2022-11-13 Philipp Tomsich New
[v2,1/2] RISC-V: Add basic support for the Ventana-VT1 core Basic support for the Ventana VT1 w/ instruction fusion - - - - --- 2022-11-13 Philipp Tomsich New
[v2,2/2] RISC-V: Add instruction fusion (for ventana-vt1) Basic support for the Ventana VT1 w/ instruction fusion - - - - --- 2022-11-13 Philipp Tomsich New
RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + addi RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + addi - - - - --- 2022-11-13 Philipp Tomsich New
RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori - - - - --- 2022-11-13 Philipp Tomsich New
RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs - - - - --- 2022-11-13 Philipp Tomsich New
[v2,1/8] RISC-V: Recognize xventanacondops extension RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - - --- 2022-11-13 Philipp Tomsich New
[v2,2/8] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - - --- 2022-11-13 Philipp Tomsich New
[v2,3/8] RISC-V: Support noce_try_store_flag_mask as vt.maskc<n> RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - - --- 2022-11-13 Philipp Tomsich New
[v2,4/8] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - - --- 2022-11-13 Philipp Tomsich New
[v2,5/8] RISC-V: Recognize bexti in negated if-conversion RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - - --- 2022-11-13 Philipp Tomsich New
[v2,6/8] RISC-V: Support immediates in XVentanaCondOps RISC-V: Backend support for XVentanaCondOps/ZiCondops - - 1 - --- 2022-11-13 Philipp Tomsich New
[v2,7/8] RISC-V: Ventana-VT1 supports XVentanaCondOps RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - - --- 2022-11-13 Philipp Tomsich New
[v2,8/8] ifcvt: add if-conversion to conditional-zero instructions RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - - --- 2022-11-13 Philipp Tomsich New
[v2] aarch64: Add support for Ampere-1A (-mcpu=ampere1a) CPU [v2] aarch64: Add support for Ampere-1A (-mcpu=ampere1a) CPU - - - - --- 2022-11-14 Philipp Tomsich New
GCC13: aarch64: Document new cores GCC13: aarch64: Document new cores - - - - --- 2022-11-14 Philipp Tomsich New
[v2] gcc-13: aarch64: Document new cores [v2] gcc-13: aarch64: Document new cores - - - - --- 2022-11-14 Philipp Tomsich New
[v2,1/2] RISC-V: Use bseti/bclri/binvi to extend reach of ori/andi/xori Use Zbs with xori/ori/andi and polarity-reversed twobit-tests - - - - --- 2022-11-18 Philipp Tomsich New
[v2,2/2] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs Use Zbs with xori/ori/andi and polarity-reversed twobit-tests - - - - --- 2022-11-18 Philipp Tomsich New
[PR107786,COMMITTED] RISC-V: Fix ICE in branch<ANYI:mode>_shiftedarith_equals_zero [PR107786,COMMITTED] RISC-V: Fix ICE in branch<ANYI:mode>_shiftedarith_equals_zero - - - - --- 2022-11-21 Philipp Tomsich New
aarch64: Update Ampere-1A (-mcpu=ampere1a) to include SM4 aarch64: Update Ampere-1A (-mcpu=ampere1a) to include SM4 - - - - --- 2023-01-28 Philipp Tomsich New
[COMMITTED] PR target/108589 - Check REG_P for AARCH64_FUSE_ADDSUB_2REG_CONST1 [COMMITTED] PR target/108589 - Check REG_P for AARCH64_FUSE_ADDSUB_2REG_CONST1 - - - - --- 2023-01-31 Philipp Tomsich New
[RFC,v1,01/10] docs: Document a canonical RTL for a conditional-zero insns [RFC,v1,01/10] docs: Document a canonical RTL for a conditional-zero insns - - - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,02/10] RISC-V: Recognize Zicond (conditional operations) extension [RFC,v1,01/10] docs: Document a canonical RTL for a conditional-zero insns - - - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,03/10] RISC-V: Generate czero.eqz/nez on noce_try_store_flag_mask if-conversion [RFC,v1,01/10] docs: Document a canonical RTL for a conditional-zero insns - - - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,04/10] RISC-V: Support immediates in Zicond [RFC,v1,01/10] docs: Document a canonical RTL for a conditional-zero insns - - - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,05/10] RISC-V: Support noce_try_store_flag_mask as czero.eqz/czero.nez [RFC,v1,01/10] docs: Document a canonical RTL for a conditional-zero insns - - - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,06/10] RISC-V: Recognize sign-extract + and cases for czero.eqz/nez [RFC,v1,01/10] docs: Document a canonical RTL for a conditional-zero insns - - - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,07/10] RISC-V: Recognize bexti in negated if-conversion [RFC,v1,01/10] docs: Document a canonical RTL for a conditional-zero insns - - - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,08/10] ifcvt: add if-conversion to conditional-zero instructions [RFC,v1,01/10] docs: Document a canonical RTL for a conditional-zero insns - - - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,09/10] RISC-V: Recognize xventanacondops extension [RFC,v1,01/10] docs: Document a canonical RTL for a conditional-zero insns - - - - --- 2023-02-10 Philipp Tomsich New
[RFC,v1,10/10] RISC-V: Support XVentanaCondOps extension [RFC,v1,01/10] docs: Document a canonical RTL for a conditional-zero insns - - - - --- 2023-02-10 Philipp Tomsich New
aarch64: update ampere1 vectorization cost aarch64: update ampere1 vectorization cost - - - - --- 2023-03-27 Philipp Tomsich New
aarch64: disable LDP via tuning structure for -mcpu=ampere1 aarch64: disable LDP via tuning structure for -mcpu=ampere1 - - - - --- 2023-04-13 Philipp Tomsich New
[v2] aarch64: disable LDP via tuning structure for -mcpu=ampere1/1a [v2] aarch64: disable LDP via tuning structure for -mcpu=ampere1/1a - - - - --- 2023-04-14 Philipp Tomsich New
cprop_hardreg: fix ORIGINAL_REGNO/REG_ATTRS/REG_POINTER handling cprop_hardreg: fix ORIGINAL_REGNO/REG_ATTRS/REG_POINTER handling - 1 - - --- 2023-06-22 Philipp Tomsich New
[COMMITTED,PR,110308] cprop_hardreg: fix ORIGINAL_REGNO/REG_ATTRS/REG_POINTER handling [COMMITTED,PR,110308] cprop_hardreg: fix ORIGINAL_REGNO/REG_ATTRS/REG_POINTER handling - 1 - - --- 2023-06-28 Philipp Tomsich New
aarch64: costs: update for TARGET_CSSC aarch64: costs: update for TARGET_CSSC - - - - --- 2023-11-16 Philipp Tomsich New
aarch64: Add support for Ampere-1B (-mcpu=ampere1b) CPU aarch64: Add support for Ampere-1B (-mcpu=ampere1b) CPU - - - - --- 2023-11-16 Philipp Tomsich New
[v2] aarch64: Add support for Ampere-1B (-mcpu=ampere1b) CPU [v2] aarch64: Add support for Ampere-1B (-mcpu=ampere1b) CPU - - - - --- 2023-11-23 Philipp Tomsich New
Fix obvious typo in microblaze.opt - - - - --- 2011-01-04 Philipp Thomas New
config/mep/mep.c: don't translate syntax description. - - - - --- 2011-05-04 Philipp Thomas New
[PING] config/mep/mep.c: don't translate syntax description. - - - - --- 2011-05-06 Philipp Thomas New
libstdc++: Add pretty printer for std::span libstdc++: Add pretty printer for std::span - - - - --- 2022-04-04 Philipp Fent New
libstdc++: Add pretty printer for std::initializer_list libstdc++: Add pretty printer for std::initializer_list - - - - --- 2022-04-24 Philipp Fent New
[1/2] libstdc++: Fix pretty printer tests of tuple indexes [1/2] libstdc++: Fix pretty printer tests of tuple indexes - - - - --- 2022-09-04 Philipp Fent New
[2/2] libstdc++: Add pretty printer for std::stringstream [1/2] libstdc++: Fix pretty printer tests of tuple indexes - - - - --- 2022-09-04 Philipp Fent New
[v2] libstdc++: Add pretty printer for std::stringstreams [v2] libstdc++: Add pretty printer for std::stringstreams - - - - --- 2022-09-06 Philipp Fent New
Remove Flag syntax only in c-decl.c write_globals - - - - --- 2010-06-19 Philip Herron New
Objective C/C++ Compiler Drivers - - - - --- 2010-08-18 Philip Herron New
Partial Transition fix attempt - - - - --- 2012-03-21 Philip Herron New
Simple install hook - - - - --- 2014-02-11 Philip Herron New
Extract a common logger from jit and analyzer frameworks Extract a common logger from jit and analyzer frameworks - - - - --- 2021-03-04 Philip Herron New
[v2] Extract a common logger the analyzer framework [v2] Extract a common logger the analyzer framework - - - - --- 2021-03-08 Philip Herron New
[Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,02/37] gccrs: Add nessecary hooks for a Rust front-end testsuite [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,03/37] gccrs: Add Debug info testsuite [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,04/37] gccrs: Add link cases testsuite [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,05/37] gccrs: Add general compilation test cases [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,06/37] gccrs: Add execution test cases [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,07/37] gccrs: Add gcc-check-target check-rust [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,09/37] gccrs: Add Lexer for Rust front-end [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,11/37] gccrs: Add expansion pass for the Rust front-end [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,12/37] gccrs: Add name resolution pass to the Rust front-end [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,14/37] gccrs: Add AST to HIR lowering pass [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,15/37] gccrs: Add wrapper for make_unique [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,16/37] gccrs: Add port of FNV hash used during legacy symbol mangling [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,17/37] gccrs: Add Rust ABI enum helpers [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,18/37] gccrs: Add Base62 implementation [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,19/37] gccrs: Add implementation of Optional [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,20/37] gccrs: Add attributes checker [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
[Rust,front-end,v2,21/37] gccrs: Add helpers mappings canonical path and lang items [Rust,front-end,v2,01/37] Use DW_ATE_UTF for the Rust 'char' type - - - - --- 2022-08-24 Philip Herron New
« 1 2 ... 366 367 368 … 1269 1270 »