| Message ID | 20221108200323.2719563-1-philipp.tomsich@vrull.eu |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: allow bseti on SImode without sign-extension | expand |
On 11/8/22 13:03, Philipp Tomsich wrote: > As long as the SImode operand is not a partial subreg, we can use a > bseti without postprocessing to or in a bit, as the middle end is > smart enough to stay away from the signbit. > > gcc/ChangeLog: > > * config/riscv/bitmanip.md (*bsetidisi): New pattern. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/zbs-bexti-02.c: New test. OK, with my usual grumble about SUBREGs. jeff
Applied to master. Thanks! Philipp. On Fri, 18 Nov 2022 at 20:26, Jeff Law <jeffreyalaw@gmail.com> wrote: > > On 11/8/22 13:03, Philipp Tomsich wrote: > > As long as the SImode operand is not a partial subreg, we can use a > > bseti without postprocessing to or in a bit, as the middle end is > > smart enough to stay away from the signbit. > > > > gcc/ChangeLog: > > > > * config/riscv/bitmanip.md (*bsetidisi): New pattern. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/zbs-bexti-02.c: New test. > > OK, with my usual grumble about SUBREGs. > > jeff > > >
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index cbc00455b67..dddd3422c43 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -408,6 +408,18 @@ "bseti\t%0,%1,%S2" [(set_attr "type" "bitmanip")]) +;; As long as the SImode operand is not a partial subreg, we can use a +;; bseti without postprocessing, as the middle end is smart enough to +;; stay away from the signbit. +(define_insn "*bsetidisi" + [(set (match_operand:DI 0 "register_operand" "=r") + (ior:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) + (match_operand 2 "single_bit_mask_operand" "i")))] + "TARGET_ZBS && TARGET_64BIT + && !partial_subreg_p (operands[2])" + "bseti\t%0,%1,%S2" + [(set_attr "type" "bitmanip")]) + (define_insn "*bclr<mode>" [(set (match_operand:X 0 "register_operand" "=r") (and:X (rotate:X (const_int -2) diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c b/gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c new file mode 100644 index 00000000000..d3629946375 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +/* bexti */ +int f(int* a, int b) +{ + return ((*a << b) | (1 << 14)); +} + +int g(int a, int b) +{ + return ((a + b)| (1 << 30)); +} + +int h(int a, int b) +{ + return ((a + b)| (1ULL << 33)); +} + +/* { dg-final { scan-assembler-times "addw\t" 2 } } */ +/* { dg-final { scan-assembler-times "sllw\t" 1 } } */ +/* { dg-final { scan-assembler-times "bseti\t" 2 } } */ +/* { dg-final { scan-assembler-not "sext.w\t" } } */ +
As long as the SImode operand is not a partial subreg, we can use a bseti without postprocessing to or in a bit, as the middle end is smart enough to stay away from the signbit. gcc/ChangeLog: * config/riscv/bitmanip.md (*bsetidisi): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbs-bexti-02.c: New test. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> --- gcc/config/riscv/bitmanip.md | 12 +++++++++ gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c | 25 +++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c