| Message ID | 20230210224150.2801962-8-philipp.tomsich@vrull.eu |
|---|---|
| State | New |
| Headers | show |
| Series | [RFC,v1,01/10] docs: Document a canonical RTL for a conditional-zero insns | expand |
On 2/10/23 15:41, Philipp Tomsich wrote: > While the positive case "if ((bits >> SHAMT) & 1)" for SHAMT 0..10 can > trigger conversion into efficient branchless sequences > - with Zbs (bexti + neg + and) > - with Zicond (andi + czero.nez) > the inverted/negated case results in > andi a5,a0,1024 > seqz a5,a5 > neg a5,a5 > and a5,a5,a1 > due to how the sequence presents to the combine pass. > > This adds an additional splitter to reassociate the polarity reversed > case into bexti + addi, if Zbs is present. > > gcc/ChangeLog: > > * config/riscv/zicond.md: Add split to reassociate > "andi + seqz + neg" into "bexti + addi". OK. jeff
diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md index 15fdaa539f1..0aad61c7009 100644 --- a/gcc/config/riscv/zicond.md +++ b/gcc/config/riscv/zicond.md @@ -143,3 +143,13 @@ (define_split { operands[2] = GEN_INT(1 << UINTVAL(operands[2])); }) + +(define_split + [(set (match_operand:X 0 "register_operand") + (neg:X (eq:X (zero_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (const_int 0))))] + "!TARGET_ZICOND && TARGET_ZBS" + [(set (match_dup 0) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (plus:X (match_dup 0) (const_int -1)))])
While the positive case "if ((bits >> SHAMT) & 1)" for SHAMT 0..10 can trigger conversion into efficient branchless sequences - with Zbs (bexti + neg + and) - with Zicond (andi + czero.nez) the inverted/negated case results in andi a5,a0,1024 seqz a5,a5 neg a5,a5 and a5,a5,a1 due to how the sequence presents to the combine pass. This adds an additional splitter to reassociate the polarity reversed case into bexti + addi, if Zbs is present. gcc/ChangeLog: * config/riscv/zicond.md: Add split to reassociate "andi + seqz + neg" into "bexti + addi". Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> --- gcc/config/riscv/zicond.md | 10 ++++++++++ 1 file changed, 10 insertions(+)