| Message ID | 20240331202921.262323-2-jonas@kwiboo.se |
|---|---|
| State | Changes Requested |
| Delegated to: | Kever Yang |
| Headers | show |
| Series | rockchip: rk3399: Sync DT with linux v6.8 and update defconfigs | expand |
On 2024/4/1 04:28, Jonas Karlman wrote: > Chromebook bob and kevin only use SPL and not TPL+SPL like other RK3399 > boards, this mean that SPL is loaded to and run from SRAM instead of > DRAM. The SPL and U-Boot payload is loaded from SPI flash. > > The U-Boot payload is located at 0x40000 (256 KiB) offset in SPI flash > and because the BROM only read first 2 KiB for each 4 KiB page, the size > of SPL (idbloader.img) is limited to max 128 KiB. > > The chosen bss start address further limits the size of SPL to 120 KiB. > > 0xff8e0000 (SPL_BSS_START_ADDR) - 0xff8c2000 (SPL_TEXT_BASE) = 0x1e000 > > Update SPL_MAX_SIZE to reflect the 120 KiB max size limitation. > > Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Thanks, - Kever > --- > configs/chromebook_bob_defconfig | 2 +- > configs/chromebook_kevin_defconfig | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig > index d0321948697b..58e76f11472c 100644 > --- a/configs/chromebook_bob_defconfig > +++ b/configs/chromebook_bob_defconfig > @@ -30,7 +30,7 @@ CONFIG_BOARD_EARLY_INIT_R=y > CONFIG_BLOBLIST=y > CONFIG_BLOBLIST_ADDR=0x100000 > CONFIG_BLOBLIST_SIZE=0x1000 > -CONFIG_SPL_MAX_SIZE=0x2e000 > +CONFIG_SPL_MAX_SIZE=0x1e000 > CONFIG_SPL_PAD_TO=0x7f8000 > CONFIG_SPL_HAS_BSS_LINKER_SECTION=y > CONFIG_SPL_BSS_START_ADDR=0xff8e0000 > diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig > index 120c11c04972..5adc276a746a 100644 > --- a/configs/chromebook_kevin_defconfig > +++ b/configs/chromebook_kevin_defconfig > @@ -31,7 +31,7 @@ CONFIG_BOARD_EARLY_INIT_R=y > CONFIG_BLOBLIST=y > CONFIG_BLOBLIST_ADDR=0x100000 > CONFIG_BLOBLIST_SIZE=0x1000 > -CONFIG_SPL_MAX_SIZE=0x2e000 > +CONFIG_SPL_MAX_SIZE=0x1e000 > CONFIG_SPL_PAD_TO=0x7f8000 > CONFIG_SPL_HAS_BSS_LINKER_SECTION=y > CONFIG_SPL_BSS_START_ADDR=0xff8e0000
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index d0321948697b..58e76f11472c 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -30,7 +30,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x1e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0xff8e0000 diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 120c11c04972..5adc276a746a 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -31,7 +31,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x1e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0xff8e0000
Chromebook bob and kevin only use SPL and not TPL+SPL like other RK3399 boards, this mean that SPL is loaded to and run from SRAM instead of DRAM. The SPL and U-Boot payload is loaded from SPI flash. The U-Boot payload is located at 0x40000 (256 KiB) offset in SPI flash and because the BROM only read first 2 KiB for each 4 KiB page, the size of SPL (idbloader.img) is limited to max 128 KiB. The chosen bss start address further limits the size of SPL to 120 KiB. 0xff8e0000 (SPL_BSS_START_ADDR) - 0xff8c2000 (SPL_TEXT_BASE) = 0x1e000 Update SPL_MAX_SIZE to reflect the 120 KiB max size limitation. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> --- configs/chromebook_bob_defconfig | 2 +- configs/chromebook_kevin_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)