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[13/31] clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock

Message ID 20240331202921.262323-14-jonas@kwiboo.se
State Changes Requested
Delegated to: Kever Yang
Headers show
Series rockchip: rk3399: Sync DT with linux v6.8 and update defconfigs | expand

Commit Message

Jonas Karlman March 31, 2024, 8:28 p.m. UTC 
rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the
SCLK_PCIEPHY_REF clock.

The existing enable/disable ops for SCLK_PCIEPHY_REF already handles
setting correct parent once the clock gets enabled. And 100 MHz is the
default rate used for this clock.

Add dummy support for setting parent, getting and setting clock rate of
the SCLK_PCIEPHY_REF clock to allow use of PCIe on affected boards.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
 drivers/clk/rockchip/clk_rk3399.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Quentin Schulz April 2, 2024, 2:44 p.m. UTC | #1 
Hi Jonas,

On 3/31/24 22:28, Jonas Karlman wrote:
> rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the
> SCLK_PCIEPHY_REF clock.
> 
> The existing enable/disable ops for SCLK_PCIEPHY_REF already handles
> setting correct parent once the clock gets enabled. And 100 MHz is the
> default rate used for this clock.
> 

I'm not sure that's true?

If I read the TRM correctly, clk_pciephy_ref_sel can come either from 
clk_pcie_ref24m (the default) or clk_pcie_ref100m.

enable/disable is actually only ever writing 0 to that bit (bit 10 in 
CRU_CLKSEL_CON18) and not even enabling the clock.

Assuming clk_pcie_ref24m is the 24MHz base clock (which seems to be the 
case according to the Linux kernel CRU driver), there shouldn't be a way 
to disable that clock. However, if clk_pcie_ref100m is selected, one 
needs to enable/disable it via CRU_CLKGATE_CON12 bit 6 (enabled by default).

set_parent should be properly implemented to handle this parenting and 
enable/disable fixed to use the proper register.

Cheers,
Quentin
Kever Yang April 23, 2024, 11:03 a.m. UTC | #2 
On 2024/4/1 04:28, Jonas Karlman wrote:
> rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the
> SCLK_PCIEPHY_REF clock.
>
> The existing enable/disable ops for SCLK_PCIEPHY_REF already handles
> setting correct parent once the clock gets enabled. And 100 MHz is the
> default rate used for this clock.
>
> Add dummy support for setting parent, getting and setting clock rate of
> the SCLK_PCIEPHY_REF clock to allow use of PCIe on affected boards.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/clk/rockchip/clk_rk3399.c | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 5934771b4096..29b01abeca06 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -972,6 +972,7 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
>   	case ACLK_GIC_PRE:
>   	case PCLK_DDR:
>   	case ACLK_VDU:
> +	case SCLK_PCIEPHY_REF:
>   		break;
>   	case PCLK_ALIVE:
>   	case PCLK_WDT:
> @@ -1063,6 +1064,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
>   	case ACLK_GIC_PRE:
>   	case PCLK_DDR:
>   	case ACLK_VDU:
> +	case SCLK_PCIEPHY_REF:
>   		return 0;
>   	default:
>   		log_debug("Unknown clock %lu\n", clk->id);
> @@ -1114,6 +1116,8 @@ static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
>   	switch (clk->id) {
>   	case SCLK_RMII_SRC:
>   		return rk3399_gmac_set_parent(clk, parent);
> +	case SCLK_PCIEPHY_REF:
> +		return 0;
>   	}
>   
>   	debug("%s: unsupported clk %ld\n", __func__, clk->id);
diff mbox series

Patch

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 5934771b4096..29b01abeca06 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -972,6 +972,7 @@  static ulong rk3399_clk_get_rate(struct clk *clk)
 	case ACLK_GIC_PRE:
 	case PCLK_DDR:
 	case ACLK_VDU:
+	case SCLK_PCIEPHY_REF:
 		break;
 	case PCLK_ALIVE:
 	case PCLK_WDT:
@@ -1063,6 +1064,7 @@  static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 	case ACLK_GIC_PRE:
 	case PCLK_DDR:
 	case ACLK_VDU:
+	case SCLK_PCIEPHY_REF:
 		return 0;
 	default:
 		log_debug("Unknown clock %lu\n", clk->id);
@@ -1114,6 +1116,8 @@  static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
 	switch (clk->id) {
 	case SCLK_RMII_SRC:
 		return rk3399_gmac_set_parent(clk, parent);
+	case SCLK_PCIEPHY_REF:
+		return 0;
 	}
 
 	debug("%s: unsupported clk %ld\n", __func__, clk->id);