diff mbox series

[v2,7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()

Message ID 20211030135513.18517-8-bin.meng@windriver.com
State Superseded
Headers show
Series target/riscv: Initial support for native debug feature via M-mode CSRs | expand

Commit Message

Bin Meng Oct. 30, 2021, 1:55 p.m. UTC 
This is now used by RISC-V as well. Update the comments.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

---

(no changes since v1)

 include/hw/core/tcg-cpu-ops.h | 1 +
 1 file changed, 1 insertion(+)

Comments

Alistair Francis Nov. 3, 2021, 6 a.m. UTC | #1 
On Sun, Oct 31, 2021 at 12:02 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> This is now used by RISC-V as well. Update the comments.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> ---
>
> (no changes since v1)
>
>  include/hw/core/tcg-cpu-ops.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
> index 6cbe17f2e6..532c148a80 100644
> --- a/include/hw/core/tcg-cpu-ops.h
> +++ b/include/hw/core/tcg-cpu-ops.h
> @@ -92,6 +92,7 @@ struct TCGCPUOps {
>      /**
>       * @debug_check_watchpoint: return true if the architectural
>       * watchpoint whose address has matched should really fire, used by ARM
> +     * and RISC-V
>       */
>      bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
>
> --
> 2.25.1
>
>
diff mbox series

Patch

diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 6cbe17f2e6..532c148a80 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -92,6 +92,7 @@  struct TCGCPUOps {
     /**
      * @debug_check_watchpoint: return true if the architectural
      * watchpoint whose address has matched should really fire, used by ARM
+     * and RISC-V
      */
     bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);