Show patches with: Submitter = Bin Meng       |    State = Action Required       |    Archived = No       |   384 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[9/9] hw/9p: win32: Translate Windows error number to Linux value 9pfs: Add 9pfs support for Windows host - - - - --- 2022-04-25 Bin Meng New
[8/9] meson.build: Turn on virtfs for Windows host 9pfs: Add 9pfs support for Windows host - - - - --- 2022-04-25 Bin Meng New
[7/9] fsdev: Enable 'local' file system driver backend for Windows 9pfs: Add 9pfs support for Windows host - - - - --- 2022-04-25 Bin Meng New
[6/9] hw/9pfs: Update 9p-synth.c for Windows build 9pfs: Add 9pfs support for Windows host - - - - --- 2022-04-25 Bin Meng New
[5/9] hw/9pfs: Add a 'local' file system backend driver for Windows 9pfs: Add 9pfs support for Windows host - - - - --- 2022-04-25 Bin Meng New
[4/9] fsdev: Add missing definitions for Windows in file-op-9p.h 9pfs: Add 9pfs support for Windows host - - - - --- 2022-04-25 Bin Meng New
[3/9] hw/9pfs: Extract common stuff to 9p-local.h 9pfs: Add 9pfs support for Windows host - - - - --- 2022-04-25 Bin Meng New
[2/9] qemu/xatth.h: Update for Windows build 9pfs: Add 9pfs support for Windows host - - - - --- 2022-04-25 Bin Meng New
[1/9] hw/9pfs: Compile 9p-local.c and 9p-proxy.c for Linux and macOS 9pfs: Add 9pfs support for Windows host - - - - --- 2022-04-25 Bin Meng New
[2/2] hw/riscv: Don't add empty bootargs to device tree [1/2] hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally - 1 1 - --- 2022-04-21 Bin Meng New
[1/2] hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally [1/2] hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally - 1 1 - --- 2022-04-21 Bin Meng New
[v2] target/ppc: Fix BookE debug interrupt generation [v2] target/ppc: Fix BookE debug interrupt generation - - 3 - --- 2022-04-21 Bin Meng New
[v5,6/6] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() target/riscv: Initial support for the Sdtrig extension via M-mode CSRs - - 2 - --- 2022-04-21 Bin Meng New
[v5,5/6] target/riscv: cpu: Enable native debug feature target/riscv: Initial support for the Sdtrig extension via M-mode CSRs - - 1 - --- 2022-04-21 Bin Meng New
[v5,4/6] target/riscv: machine: Add debug state description target/riscv: Initial support for the Sdtrig extension via M-mode CSRs - - 1 - --- 2022-04-21 Bin Meng New
[v5,3/6] target/riscv: csr: Hook debug CSR read/write target/riscv: Initial support for the Sdtrig extension via M-mode CSRs - - 1 - --- 2022-04-21 Bin Meng New
[v5,2/6] target/riscv: cpu: Add a config option for native debug target/riscv: Initial support for the Sdtrig extension via M-mode CSRs - - 1 - --- 2022-04-21 Bin Meng New
[v5,1/6] target/riscv: debug: Implement debug related TCGCPUOps target/riscv: Initial support for the Sdtrig extension via M-mode CSRs - - 1 - --- 2022-04-21 Bin Meng New
target/ppc: Fix BookE debug interrupt generation target/ppc: Fix BookE debug interrupt generation - - - - --- 2022-04-20 Bin Meng New
[v2,2/2] hw/core: loader: Set is_linux to true for VxWorks uImage [v2,1/2] hw/core: Sync uboot_image.h from U-Boot v2022.01 - - 2 - --- 2022-03-24 Bin Meng New
[v2,1/2] hw/core: Sync uboot_image.h from U-Boot v2022.01 [v2,1/2] hw/core: Sync uboot_image.h from U-Boot v2022.01 - - - - --- 2022-03-24 Bin Meng New
[2/2] hw/core: loader: Setting is_linux to true for VxWorks uImage [1/2] hw/core: Sync uboot_image.h from U-Boot v2022.01 - - 1 - --- 2022-03-24 Bin Meng New
[1/2] hw/core: Sync uboot_image.h from U-Boot v2022.01 [1/2] hw/core: Sync uboot_image.h from U-Boot v2022.01 - - 1 - --- 2022-03-24 Bin Meng New
[2/2] monitor/misc: Set current_cpu for memory dump [1/2] gdbstub: Set current_cpu for memory read write - - - - --- 2022-03-22 Bin Meng New
[1/2] gdbstub: Set current_cpu for memory read write [1/2] gdbstub: Set current_cpu for memory read write - - - - --- 2022-03-22 Bin Meng New
target/avr: Drop avr_cpu_memory_rw_debug() target/avr: Drop avr_cpu_memory_rw_debug() - - 1 - --- 2022-03-22 Bin Meng New
[v4,1/7] target/riscv: Add initial support for the Sdtrig extension target/riscv: Initial support for the Sdtrig extension via M-mode CSRs - - 1 - --- 2022-03-15 Bin Meng New
roms/opensbi: Upgrade from v0.9 to v1.0 roms/opensbi: Upgrade from v0.9 to v1.0 - - 1 - --- 2022-01-05 Bin Meng New
target/riscv: machine: Sort the .subsections target/riscv: machine: Sort the .subsections - - 1 - --- 2021-10-30 Bin Meng New
[v2,6/6] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines - - 3 - --- 2021-10-20 Bin Meng New
[v2,5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines - - 3 - --- 2021-10-20 Bin Meng New
[v2,4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines - - 3 - --- 2021-10-20 Bin Meng New
[v2,3/6] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines - - 3 - --- 2021-10-20 Bin Meng New
[v2,2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines - - 3 - --- 2021-10-20 Bin Meng New
[v2,1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines - - 2 - --- 2021-10-20 Bin Meng New
[v2,2/2] hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed [v2,1/2] hw/dma: sifive_pdma: Fix Control.claim bit detection 1 - - - --- 2021-09-27 Bin Meng New
[v2,1/2] hw/dma: sifive_pdma: Fix Control.claim bit detection [v2,1/2] hw/dma: sifive_pdma: Fix Control.claim bit detection - 1 2 - --- 2021-09-27 Bin Meng New
[3/3] hw/char: sifive_uart: Register device in 'input' category [1/3] hw/char: ibex_uart: Register device in 'input' category - - 2 - --- 2021-09-26 Bin Meng New
[2/3] hw/char: shakti_uart: Register device in 'input' category [1/3] hw/char: ibex_uart: Register device in 'input' category - - 2 - --- 2021-09-26 Bin Meng New
[1/3] hw/char: ibex_uart: Register device in 'input' category [1/3] hw/char: ibex_uart: Register device in 'input' category - - 2 - --- 2021-09-26 Bin Meng New
[RESEND,3/3] hw/intc: openpic: Clean up the styles [RESEND,1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset - - - - --- 2021-09-18 Bin Meng New
[RESEND,2/3] hw/intc: openpic: Drop Raven related codes [RESEND,1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset - - - - --- 2021-09-18 Bin Meng New
[RESEND,1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset [RESEND,1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset - 1 - - --- 2021-09-18 Bin Meng New
target/riscv: csr: Rename HCOUNTEREN_CY and friends target/riscv: csr: Rename HCOUNTEREN_CY and friends - - 1 - --- 2021-09-15 Bin Meng New
docs/system/riscv: sifive_u: Update U-Boot instructions docs/system/riscv: sifive_u: Update U-Boot instructions - - 1 - --- 2021-09-11 Bin Meng New
docs/devel: memory: Document MemoryRegionOps requirement docs/devel: memory: Document MemoryRegionOps requirement - - 1 - --- 2021-09-06 Bin Meng New
softmmu/memory: Validate {read, write}_with_attrs before calling softmmu/memory: Validate {read, write}_with_attrs before calling - 1 - - --- 2021-09-05 Bin Meng New
[v3,6/6] hw/char: cadence_uart: Log a guest error when device is unclocked or in reset hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure - - 1 - --- 2021-09-01 Bin Meng New
[v3,5/6] hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure - - 1 - --- 2021-09-01 Bin Meng New
[v3,4/6] hw/char: cadence_uart: Convert to memop_with_attrs() ops hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure - - 1 - --- 2021-09-01 Bin Meng New
[v3,3/6] hw/char: cadence_uart: Move clock/reset check to uart_can_receive() hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure - - 1 - --- 2021-09-01 Bin Meng New
[v3,2/6] hw/char: cadence_uart: Disable transmit when input clock is disabled hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure - 1 1 - --- 2021-09-01 Bin Meng New
[v3,1/6] hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure 1 1 1 - --- 2021-09-01 Bin Meng New
[v2,5/5] hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure - - 1 - --- 2021-09-01 Bin Meng New
[v2,4/5] hw/char: cadence_uart: Convert to memop_with_attrs() ops hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure - - 1 - --- 2021-09-01 Bin Meng New
[v2,3/5] hw/char: cadence_uart: Move clock/reset check to uart_can_receive() hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure - - 2 - --- 2021-09-01 Bin Meng New
[v2,2/5] hw/char: cadence_uart: Disable transmit when input clock is disabled hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure - 1 1 - --- 2021-09-01 Bin Meng New
[v2,1/5] hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure 1 1 1 - --- 2021-09-01 Bin Meng New
[3/3] hw/char: cadence_uart: Move clock/reset check to uart_can_receive() hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure - - - - --- 2021-08-23 Bin Meng New
[2/3] hw/char: cadence_uart: Disable transmit when input clock is disabled hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure - 1 1 - --- 2021-08-23 Bin Meng New
[1/3] hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure 1 1 1 - --- 2021-08-23 Bin Meng New
[For,6.1] hw/arm: xilinx_zynq: Disconnect the UART clocks temporarily [For,6.1] hw/arm: xilinx_zynq: Disconnect the UART clocks temporarily - - - - --- 2021-08-21 Bin Meng New
tcg: Remove tcg_global_reg_new defines tcg: Remove tcg_global_reg_new defines - - 1 - --- 2021-08-16 Bin Meng New
target/riscv: Correct a comment in riscv_csrrw() target/riscv: Correct a comment in riscv_csrrw() - - 1 - --- 2021-08-07 Bin Meng New
hw/riscv: virt: Move flash node to root hw/riscv: virt: Move flash node to root - - 2 - --- 2021-08-07 Bin Meng New
[v4,3/3] hw/net: e1000e: Don't zero out the VLAN tag in the legacy RX descriptor [v4,1/3] hw/net: e1000: Correct the initial value of VET register - 1 - - --- 2021-07-23 Bin Meng New
[v4,2/3] hw/net: e1000e: Correct the initial value of VET register [v4,1/3] hw/net: e1000: Correct the initial value of VET register - - - - --- 2021-07-23 Bin Meng New
[v4,1/3] hw/net: e1000: Correct the initial value of VET register [v4,1/3] hw/net: e1000: Correct the initial value of VET register - - - - --- 2021-07-23 Bin Meng New
[v3,3/3] hw/net: e1000e: Don't zero out the VLAN tag in the legacy RX descriptor [v3,1/3] hw/net: e1000: Correct the initial value of VET register - 1 - - --- 2021-07-21 Bin Meng New
[v3,2/3] hw/net: e1000e: Correct the initial value of VET register [v3,1/3] hw/net: e1000: Correct the initial value of VET register - - - - --- 2021-07-21 Bin Meng New
[v3,1/3] hw/net: e1000: Correct the initial value of VET register [v3,1/3] hw/net: e1000: Correct the initial value of VET register - - - - --- 2021-07-21 Bin Meng New
hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned - - 1 - --- 2021-07-08 Bin Meng New
hw/riscv: sifive_u: Correct the CLINT timebase frequency hw/riscv: sifive_u: Correct the CLINT timebase frequency - - 1 - --- 2021-07-06 Bin Meng New
docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot - - 1 - --- 2021-07-06 Bin Meng New
[2/2] docs/system: ppc: Update ppce500 documentation with eTSEC support [1/2] roms/u-boot: Bump ppce500 u-boot to v2021.07 to add eTSEC support - - - - --- 2021-07-06 Bin Meng New
[1/2] roms/u-boot: Bump ppce500 u-boot to v2021.07 to add eTSEC support [1/2] roms/u-boot: Bump ppce500 u-boot to v2021.07 to add eTSEC support - - - - --- 2021-07-06 Bin Meng New
[v2,3/3] hw/net: e1000e: Don't zero out the VLAN tag in the legacy RX descriptor [v2,1/3] hw/net: e1000: Correct the initial value of VET register - 1 - - --- 2021-07-02 Bin Meng New
[v2,2/3] hw/net: e1000e: Correct the initial value of VET register [v2,1/3] hw/net: e1000: Correct the initial value of VET register - - - - --- 2021-07-02 Bin Meng New
[v2,1/3] hw/net: e1000: Correct the initial value of VET register [v2,1/3] hw/net: e1000: Correct the initial value of VET register - - - - --- 2021-07-02 Bin Meng New
[2/2] docs/system: riscv: Add documentation for virt machine [1/2] docs/system: riscv: Fix CLINT name in the sifive_u doc - - 1 - --- 2021-06-27 Bin Meng New
[1/2] docs/system: riscv: Fix CLINT name in the sifive_u doc [1/2] docs/system: riscv: Fix CLINT name in the sifive_u doc - - 1 - --- 2021-06-27 Bin Meng New
[v2] target/riscv: csr: Remove redundant check in fp csr read/write routines [v2] target/riscv: csr: Remove redundant check in fp csr read/write routines - - 1 - --- 2021-06-27 Bin Meng New
target/riscv: pmp: Fix some typos target/riscv: pmp: Fix some typos - - 2 - --- 2021-06-27 Bin Meng New
target/riscv: gdbstub: Fix dynamic CSR XML generation target/riscv: gdbstub: Fix dynamic CSR XML generation - 1 1 1 --- 2021-06-15 Bin Meng New
[2/2] hw/usb: hcd-xhci-pci: Fix spec violation of IP flag for MSI/MSI-X [1/2] hw/usb: hcd-xhci-pci: Raise MSI/MSI-X interrupts only when told to - 2 1 - --- 2021-05-21 Bin Meng New
[1/2] hw/usb: hcd-xhci-pci: Raise MSI/MSI-X interrupts only when told to [1/2] hw/usb: hcd-xhci-pci: Raise MSI/MSI-X interrupts only when told to - 1 1 - --- 2021-05-21 Bin Meng New
target/riscv: Remove unnecessary riscv_*_names[] declaration target/riscv: Remove unnecessary riscv_*_names[] declaration - - 2 - --- 2021-05-14 Bin Meng New
[v2,8/8] hw/riscv: microchip_pfsoc: Support direct kernel boot [v2,1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-04-30 Bin Meng New
[v2,7/8] hw/riscv: Use macros for BIOS image names [v2,1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-04-30 Bin Meng New
[v2,6/8] docs/system/riscv: sifive_u: Document '-dtb' usage [v2,1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-04-30 Bin Meng New
[v2,5/8] docs/system/riscv: Correct the indentation level of supported devices [v2,1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-04-30 Bin Meng New
[v2,4/8] hw/riscv: Support the official PLIC DT bindings [v2,1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-04-30 Bin Meng New
[v2,3/8] hw/riscv: Support the official CLINT DT bindings [v2,1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-04-30 Bin Meng New
[v2,2/8] hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper [v2,1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-04-30 Bin Meng New
[v2,1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper [v2,1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-04-30 Bin Meng New
docs/system: riscv: Include shakti_c machine documentation docs/system: riscv: Include shakti_c machine documentation - - 1 - --- 2021-04-30 Bin Meng New
[for-6.0,3/3] docs/system: ppc: Add documentation for ppce500 machine [for-6.0,1/3] roms/Makefile: Update ppce500 u-boot build directory name - - - - --- 2021-04-06 Bin Meng New
[for-6.0,2/3] roms/u-boot: Bump ppce500 u-boot to v2021.04 to fix broken pci support [for-6.0,1/3] roms/Makefile: Update ppce500 u-boot build directory name - - - - --- 2021-04-06 Bin Meng New
[for-6.0,1/3] roms/Makefile: Update ppce500 u-boot build directory name [for-6.0,1/3] roms/Makefile: Update ppce500 u-boot build directory name - - - - --- 2021-04-06 Bin Meng New
hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] - 1 2 - --- 2021-03-31 Bin Meng New
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