| Message ID | 20211030135513.18517-3-bin.meng@windriver.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/riscv: Initial support for native debug feature via M-mode CSRs | expand |
On Sat, Oct 30, 2021 at 11:56 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > Add a subsection to machine.c to migrate debug CSR state. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > > --- > > Changes in v2: > - new patch: add debug state description > > target/riscv/machine.c | 33 +++++++++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index ad8248ebfd..25aa3b38f7 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -164,6 +164,38 @@ static const VMStateDescription vmstate_pointermasking = { > } > }; > > +static bool debug_needed(void *opaque) > +{ > + RISCVCPU *cpu = opaque; > + CPURISCVState *env = &cpu->env; > + > + return riscv_feature(env, RISCV_FEATURE_DEBUG); > +} > + > +static const VMStateDescription vmstate_debug_type2 = { > + .name = "cpu/debug/type2", > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_UINTTL(mcontrol, trigger_type2_t), > + VMSTATE_UINTTL(maddress, trigger_type2_t), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static const VMStateDescription vmstate_debug = { > + .name = "cpu/debug", > + .version_id = 1, > + .minimum_version_id = 1, > + .needed = debug_needed, > + .fields = (VMStateField[]) { > + VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), > + VMSTATE_STRUCT_ARRAY(env.trigger_type2, RISCVCPU, TRIGGER_TYPE2_NUM, > + 0, vmstate_debug_type2, trigger_type2_t), > + VMSTATE_END_OF_LIST() > + } > +}; > + > const VMStateDescription vmstate_riscv_cpu = { > .name = "cpu", > .version_id = 3, > @@ -218,6 +250,7 @@ const VMStateDescription vmstate_riscv_cpu = { > &vmstate_hyper, > &vmstate_vector, > &vmstate_pointermasking, > + &vmstate_debug, > NULL > } > }; > -- > 2.25.1 > >
diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ad8248ebfd..25aa3b38f7 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -164,6 +164,38 @@ static const VMStateDescription vmstate_pointermasking = { } }; +static bool debug_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + + return riscv_feature(env, RISCV_FEATURE_DEBUG); +} + +static const VMStateDescription vmstate_debug_type2 = { + .name = "cpu/debug/type2", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(mcontrol, trigger_type2_t), + VMSTATE_UINTTL(maddress, trigger_type2_t), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_debug = { + .name = "cpu/debug", + .version_id = 1, + .minimum_version_id = 1, + .needed = debug_needed, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), + VMSTATE_STRUCT_ARRAY(env.trigger_type2, RISCVCPU, TRIGGER_TYPE2_NUM, + 0, vmstate_debug_type2, trigger_type2_t), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .version_id = 3, @@ -218,6 +250,7 @@ const VMStateDescription vmstate_riscv_cpu = { &vmstate_hyper, &vmstate_vector, &vmstate_pointermasking, + &vmstate_debug, NULL } };
Add a subsection to machine.c to migrate debug CSR state. Signed-off-by: Bin Meng <bin.meng@windriver.com> --- Changes in v2: - new patch: add debug state description target/riscv/machine.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)