Message ID | 20211030135513.18517-6-bin.meng@windriver.com |
---|---|
State | Superseded |
Headers | show |
Series | target/riscv: Initial support for native debug feature via M-mode CSRs | expand |
On Sun, Oct 31, 2021 at 12:03 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > This adds debug CSR read/write support to the RISC-V CSR RW table. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > --- > > (no changes since v1) > > target/riscv/cpu.c | 6 +++++ > target/riscv/csr.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 63 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 84116768ce..6f69ef4f50 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -575,6 +575,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > riscv_cpu_register_gdb_regs_for_features(cs); > > +#ifndef CONFIG_USER_ONLY > + if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { > + riscv_trigger_init(env); This function should be added here instead of patch 1 Alistair > + } > +#endif > + > qemu_init_vcpu(cs); > cpu_reset(cs); > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 9f41954894..dc47ec8d3b 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -219,6 +219,15 @@ static RISCVException epmp(CPURISCVState *env, int csrno) > > return RISCV_EXCP_ILLEGAL_INST; > } > + > +static RISCVException debug(CPURISCVState *env, int csrno) > +{ > + if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { > + return RISCV_EXCP_NONE; > + } > + > + return RISCV_EXCP_ILLEGAL_INST; > +} > #endif > > /* User Floating-Point CSRs */ > @@ -1435,6 +1444,48 @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, > return RISCV_EXCP_NONE; > } > > +static RISCVException read_tselect(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + *val = tselect_csr_read(env); > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_tselect(CPURISCVState *env, int csrno, > + target_ulong val) > +{ > + tselect_csr_write(env, val); > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException read_tdata(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + /* return 0 in tdata1 to end the trigger enumeration */ > + if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) { > + *val = 0; > + return RISCV_EXCP_NONE; > + } > + > + if (!tdata_available(env, csrno - CSR_TDATA1)) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > + > + *val = tdata_csr_read(env, csrno - CSR_TDATA1); > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_tdata(CPURISCVState *env, int csrno, > + target_ulong val) > +{ > + if (!tdata_available(env, csrno - CSR_TDATA1)) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > + > + tdata_csr_write(env, csrno - CSR_TDATA1, val); > + return RISCV_EXCP_NONE; > +} > + > /* > * Functions to access Pointer Masking feature registers > * We have to check if current priv lvl could modify > @@ -1931,6 +1982,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, > [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, > > + /* Debug CSRs */ > + [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect }, > + [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata }, > + [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata }, > + [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, > + > /* User Pointer Masking */ > [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, > [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, > -- > 2.25.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 84116768ce..6f69ef4f50 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -575,6 +575,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) riscv_cpu_register_gdb_regs_for_features(cs); +#ifndef CONFIG_USER_ONLY + if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + riscv_trigger_init(env); + } +#endif + qemu_init_vcpu(cs); cpu_reset(cs); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9f41954894..dc47ec8d3b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -219,6 +219,15 @@ static RISCVException epmp(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } + +static RISCVException debug(CPURISCVState *env, int csrno) +{ + if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} #endif /* User Floating-Point CSRs */ @@ -1435,6 +1444,48 @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static RISCVException read_tselect(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = tselect_csr_read(env); + return RISCV_EXCP_NONE; +} + +static RISCVException write_tselect(CPURISCVState *env, int csrno, + target_ulong val) +{ + tselect_csr_write(env, val); + return RISCV_EXCP_NONE; +} + +static RISCVException read_tdata(CPURISCVState *env, int csrno, + target_ulong *val) +{ + /* return 0 in tdata1 to end the trigger enumeration */ + if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) { + *val = 0; + return RISCV_EXCP_NONE; + } + + if (!tdata_available(env, csrno - CSR_TDATA1)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + *val = tdata_csr_read(env, csrno - CSR_TDATA1); + return RISCV_EXCP_NONE; +} + +static RISCVException write_tdata(CPURISCVState *env, int csrno, + target_ulong val) +{ + if (!tdata_available(env, csrno - CSR_TDATA1)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + tdata_csr_write(env, csrno - CSR_TDATA1, val); + return RISCV_EXCP_NONE; +} + /* * Functions to access Pointer Masking feature registers * We have to check if current priv lvl could modify @@ -1931,6 +1982,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, + /* Debug CSRs */ + [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect }, + [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata }, + [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata }, + [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, + /* User Pointer Masking */ [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask },
This adds debug CSR read/write support to the RISC-V CSR RW table. Signed-off-by: Bin Meng <bin.meng@windriver.com> --- (no changes since v1) target/riscv/cpu.c | 6 +++++ target/riscv/csr.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+)