Show patches with: Submitter = Alistair Francis       |    State = Action Required       |    Archived = No       |   1787 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,48/48] hw/riscv: riscv-iommu: Re-process command queue after clearing CMD_ILL [PULL,01/48] target/riscv: Remove spike as default machine - - 3 - --- 2026-05-22 Alistair Francis New
[PULL,47/48] hw/intc: riscv_aplic: add trace events of APLIC read/write function [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,46/48] hw/intc: riscv_imsic: Add reset API to IMSIC [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,45/48] hw/intc: riscv_aplic: Add reset API to APLIC [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,44/48] hw/intc: riscv_aplic: Fix level trigger IRQ in direct delivery mode [PULL,01/48] target/riscv: Remove spike as default machine - - 2 - --- 2026-05-22 Alistair Francis New
[PULL,43/48] target/riscv: Make hpmcounterh return the upper 32-bits [PULL,01/48] target/riscv: Remove spike as default machine - 1 1 - --- 2026-05-22 Alistair Francis New
[PULL,42/48] hw/riscv/virt-acpi-build: Fix off-by-one error in RIMT ID mapping [PULL,01/48] target/riscv: Remove spike as default machine 1 - - - --- 2026-05-22 Alistair Francis New
[PULL,41/48] target/riscv/csr.c: fix read of pmpaddr(0-63) CSRs [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,40/48] hw/riscv/riscv-iommu: Fix IOCOUNTINH.CY toggle detection [PULL,01/48] target/riscv: Remove spike as default machine - 1 2 - --- 2026-05-22 Alistair Francis New
[PULL,39/48] target/riscv/cpu: remove riscv_cpu_* arrays [PULL,01/48] target/riscv: Remove spike as default machine 1 - - - --- 2026-05-22 Alistair Francis New
[PULL,38/48] target/riscv/tcg: use isa_edata_arr[] to create user props [PULL,01/48] target/riscv: Remove spike as default machine 1 - - - --- 2026-05-22 Alistair Francis New
[PULL,37/48] target/riscv: do not set defaults in cpu prop callback [PULL,01/48] target/riscv: Remove spike as default machine 1 - - - --- 2026-05-22 Alistair Francis New
[PULL,36/48] target/riscv/tcg: use cfg_offset as cpu_set_multi_ext cb opaque [PULL,01/48] target/riscv: Remove spike as default machine 1 - - - --- 2026-05-22 Alistair Francis New
[PULL,35/48] target/riscv/tcg: use isa_edata_arr[] to enable max exts [PULL,01/48] target/riscv: Remove spike as default machine 1 - - - --- 2026-05-22 Alistair Francis New
[PULL,34/48] target/riscv/kvm: use isa_edata_arr[] for unavailable props [PULL,01/48] target/riscv: Remove spike as default machine 1 - - - --- 2026-05-22 Alistair Francis New
[PULL,33/48] target/riscv/tcg: use isa_edata_arr[] in riscv_cpu_update_misa_x() [PULL,01/48] target/riscv: Remove spike as default machine 1 - - - --- 2026-05-22 Alistair Francis New
[PULL,32/48] target/riscv: remove riscv_cpu_named_features[] [PULL,01/48] target/riscv: Remove spike as default machine 1 - - - --- 2026-05-22 Alistair Francis New
[PULL,31/48] target/riscv/cpu.c: remove riscv_cpu_enable_named_feat() [PULL,01/48] target/riscv: Remove spike as default machine 1 - - - --- 2026-05-22 Alistair Francis New
[PULL,30/48] target/riscv/tcg: use only isa_edata_arr[] in cpu_cfg_ext_get_name() [PULL,01/48] target/riscv: Remove spike as default machine 1 - - - --- 2026-05-22 Alistair Francis New
[PULL,29/48] target/riscv/tcg: treat all exts equally in cpu_disable_priv_spec_isa_exts [PULL,01/48] target/riscv: Remove spike as default machine 1 - - - --- 2026-05-22 Alistair Francis New
[PULL,28/48] target/riscv: make riscv-qmp-cmds use isa_data_arr[] [PULL,01/48] target/riscv: Remove spike as default machine 1 - - - --- 2026-05-22 Alistair Francis New
[PULL,27/48] target/riscv/cpu.c: fix smctr/ssctr isa_edata_arr[] order [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,26/48] target/riscv/cpu.c: add xlrbr isa_edata_arr[] entry [PULL,01/48] target/riscv: Remove spike as default machine - 1 1 - --- 2026-05-22 Alistair Francis New
[PULL,25/48] hw: misc: Implement Microchip mpfs ioscb PLLs and sysreg clock dividers [PULL,01/48] target/riscv: Remove spike as default machine 1 - - - --- 2026-05-22 Alistair Francis New
[PULL,24/48] hw/riscv/riscv-iommu: Avoid caching PCI device IDs [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,23/48] hw/riscv/riscv-iommu: fix FSC SV32 capability check [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,22/48] target/riscv/kvm: Add BFloat16 extensions support [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,21/48] target/riscv/kvm: add KVM support for Zicbop extension [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,20/48] target/riscv: clear mseccfg on reset for all dependent extensions [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,19/48] target/riscv: Update the local interrupt mask [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,18/48] target/riscv: Add mseccfg to VMStateDescription [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,17/48] target/riscv/pmp: Fix integer overflow in TOR and NA4 address computation [PULL,01/48] target/riscv: Remove spike as default machine - - 2 - --- 2026-05-22 Alistair Francis New
[PULL,16/48] target/riscv: Fix missing CDE check for scountinhibit [PULL,01/48] target/riscv: Remove spike as default machine - 1 1 - --- 2026-05-22 Alistair Francis New
[PULL,15/48] target/riscv: Remove unconditional MENVCFG_CDE from mask [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,14/48] target/riscv: add Zvknha as an implied extension for Zvknhb [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,13/48] target/riscv: Fix tail handling for vmv.s.x and vfmv.s.f [PULL,01/48] target/riscv: Remove spike as default machine 1 - - - --- 2026-05-22 Alistair Francis New
[PULL,12/48] target/riscv: Fix medeleg[11] read-only zero bit for M-mode ECALL [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,11/48] hw/char: Check interrupt after txctrl register is written [PULL,01/48] target/riscv: Remove spike as default machine - - 2 - --- 2026-05-22 Alistair Francis New
[PULL,10/48] target/riscv: rvv: Handle source overlap of vector widening reduction instructions [PULL,01/48] target/riscv: Remove spike as default machine 1 - - - --- 2026-05-22 Alistair Francis New
[PULL,09/48] hw/riscv/riscv-iommu: Fix Svnapot 64KB pages [PULL,01/48] target/riscv: Remove spike as default machine - 1 3 - --- 2026-05-22 Alistair Francis New
[PULL,08/48] target/riscv: Allow mseccfg access based on ext_zicfilp [PULL,01/48] target/riscv: Remove spike as default machine - - 3 - --- 2026-05-22 Alistair Francis New
[PULL,07/48] riscv: virt: avoid RISCVCPU copy in PMU FDT setup [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,06/48] roms/opensbi: Update to v1.8.1 [PULL,01/48] target/riscv: Remove spike as default machine - - 1 - --- 2026-05-22 Alistair Francis New
[PULL,05/48] MAINTAINERS: Maintain OpenSBI Firmware [PULL,01/48] target/riscv: Remove spike as default machine - - 2 - --- 2026-05-22 Alistair Francis New
[PULL,04/48] target/riscv: Update MISA.X for non-standard extensions [PULL,01/48] target/riscv: Remove spike as default machine - - 3 - --- 2026-05-22 Alistair Francis New
[PULL,03/48] target/riscv: Update MISA.C for Zc* extensions [PULL,01/48] target/riscv: Remove spike as default machine - - 2 - --- 2026-05-22 Alistair Francis New
[PULL,02/48] target/riscv: Deprecate the shakti_c machine [PULL,01/48] target/riscv: Remove spike as default machine - - 4 - --- 2026-05-22 Alistair Francis New
[PULL,01/48] target/riscv: Remove spike as default machine [PULL,01/48] target/riscv: Remove spike as default machine - - 3 - --- 2026-05-22 Alistair Francis New
[PULL,00/48] riscv-to-apply queue - - - - --- 2026-05-22 Alistair Francis New
target/riscv: Update the local interrupt mask target/riscv: Update the local interrupt mask - - 1 - --- 2026-05-13 Alistair Francis New
MAINTAINERS: Mark Microchip PolarFire SoC as Odd Fixes MAINTAINERS: Mark Microchip PolarFire SoC as Odd Fixes 2 - - - --- 2026-05-13 Alistair Francis New
MAINTAINERS: Maintain OpenSBI Firmware MAINTAINERS: Maintain OpenSBI Firmware - - 2 - --- 2026-05-06 Alistair Francis New
[2/2] target/riscv: Deprecate the shakti_c machine target/riscv: Update deprecated machines - - 4 - --- 2026-04-30 Alistair Francis New
[1/2] target/riscv: Remove spike as default machine target/riscv: Update deprecated machines - - 3 - --- 2026-04-30 Alistair Francis New
[PULL,51/51] target/riscv: rvv: Handle mask/source overlap of vector reduction instructions [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,50/51] target/riscv: Fix pointer masking translation mode check bug [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 2 - --- 2026-04-29 Alistair Francis New
[PULL,49/51] target/riscv: Rename riscv_pm_get_virt_pmm() to riscv_pm_get_vm_ldst_pmm() [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 2 - --- 2026-04-29 Alistair Francis New
[PULL,48/51] target/riscv: Fix pointer masking for virtual-machine load/store insns [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,47/51] target/riscv: Fix pointer masking PMM field selection logic [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 2 - --- 2026-04-29 Alistair Francis New
[PULL,46/51] target/riscv: Add a helper to return the current effective priv mode [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,45/51] target/riscv: fix address masking [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 2 - --- 2026-04-29 Alistair Francis New
[PULL,44/51] target/riscv: Use ELEN for Fractional LMUL check [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 4 - --- 2026-04-29 Alistair Francis New
[PULL,43/51] target/riscv: Don't OR mip.SEIP when mvien is one [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 2 - --- 2026-04-29 Alistair Francis New
[PULL,42/51] target/riscv: Generate access fault if sc comparison fails [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 2 - --- 2026-04-29 Alistair Francis New
[PULL,41/51] target/riscv: Mask xepc[0] only when Zc* extension is enabled [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,40/51] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated in… [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 5 - --- 2026-04-29 Alistair Francis New
[PULL,39/51] target/riscv: fix RV32 stateen CSR handling [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,38/51] hw/riscv/boot: Warn if a ELF format file is loaded as a binary [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 2 - --- 2026-04-29 Alistair Francis New
[PULL,37/51] target/riscv: tt-ascalon: Add Tenstorrent mvendorid [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 2 - --- 2026-04-29 Alistair Francis New
[PULL,36/51] target/riscv: rvv: Allow fractional LMUL on vector SHA instructions [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,35/51] target/riscv: Expose Zvfbfa extension as a cpu property [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 2 - --- 2026-04-29 Alistair Francis New
[PULL,34/51] target/riscv: rvv: Support Zvfbfa vector bf16 operations [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 2 - --- 2026-04-29 Alistair Francis New
[PULL,33/51] target/riscv: Introduce BF16 canonical NaN for Zvfbfa extension [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 3 - --- 2026-04-29 Alistair Francis New
[PULL,32/51] target/riscv: Introduce altfmt into DisasContext [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 3 - --- 2026-04-29 Alistair Francis New
[PULL,31/51] target/riscv: Use the tb->cs_base as the extend tb flags [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 2 - --- 2026-04-29 Alistair Francis New
[PULL,30/51] target/riscv: rvv: Introduce reset_ill_vtype to reset illegal vtype CSR [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 4 - --- 2026-04-29 Alistair Francis New
[PULL,29/51] target/riscv: rvv: Add new VTYPE CSR field - altfmt [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 4 - --- 2026-04-29 Alistair Francis New
[PULL,28/51] target/riscv: Add the Zvfbfa extension implied rule [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 4 - --- 2026-04-29 Alistair Francis New
[PULL,27/51] target/riscv: Add cfg properties for Zvfbfa extensions [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 4 - --- 2026-04-29 Alistair Francis New
[PULL,26/51] target/riscv: preserve RV32 henvcfgh on henvcfg writes [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,25/51] riscv_htif: reject invalid signature ranges (end <= begin) [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 2 1 --- 2026-04-29 Alistair Francis New
[PULL,24/51] hw/intc: fix heap OOB in ACLINT MTIMER multi-socket [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,23/51] target/riscv: fix stale ptshift and base on page walk restart [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - 1 1 - --- 2026-04-29 Alistair Francis New
[PULL,22/51] hw/riscv/virt-acpi-build.c: Use kvm timer frequency when kvm enabled [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - 1 1 - --- 2026-04-29 Alistair Francis New
[PULL,21/51] hw/riscv/riscv-iommu: Add IPSR.PMIP RW1C support [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 3 - --- 2026-04-29 Alistair Francis New
[PULL,20/51] hw/riscv/riscv-iommu-hpm: Fix irq_overflow_left residual value bug [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 2 - --- 2026-04-29 Alistair Francis New
[PULL,19/51] configs/targets: Forbid RISC-V to use legacy native endianness APIs [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,18/51] target/riscv: Use MO_LE for instruction fetch [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,17/51] target/riscv: Replace MO_TE -> MO_LE [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,16/51] target/riscv: Replace MO_TE by mo_endian (Zalasr extension) [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,15/51] target/riscv: Replace MO_TE by mo_endian (Zilsd extension) [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,14/51] target/riscv: Replace MO_TE by mo_endian (MIPS extension) [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,13/51] target/riscv: Have gdbstub consider CPU endianness [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,12/51] target/riscv: Expose mo_endian_env() [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,11/51] target/riscv: Simplify riscv_cpu_gdb_write_register() [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,10/51] target/riscv: Factor tiny ldn() helper in gdbstub [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,09/51] target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,08/51] target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again) [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,07/51] target/riscv: Remove MTTCG check for x-rv128 CPU model [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
[PULL,06/51] target/riscv: Make LQ and SQ use 128-bit ld/st [PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI - - 1 - --- 2026-04-29 Alistair Francis New
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