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Lehua Ding
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| 146 patches
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Apply
«
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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[COMMITTED,V3] RISC-V: Fix error combine of pred_mov pattern
[COMMITTED,V3] RISC-V: Fix error combine of pred_mov pattern
- - - -
-
-
-
2023-08-29
Lehua Ding
New
RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop}
RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop}
- - - -
-
-
-
2023-08-25
Lehua Ding
New
[V2] RISC-V: Add conditional autovec convert(INT<->INT) patterns
[V2] RISC-V: Add conditional autovec convert(INT<->INT) patterns
- - - -
-
-
-
2023-08-25
Lehua Ding
New
RISC-V: Add conditional autovec convert(INT<->FP) patterns
RISC-V: Add conditional autovec convert(INT<->FP) patterns
- - - -
-
-
-
2023-08-24
Lehua Ding
New
RISC-V: Add conditional convert autovec patterns between FPs
RISC-V: Add conditional convert autovec patterns between FPs
- - - -
-
-
-
2023-08-23
Lehua Ding
New
RISC-V: Add conditional sign/zero extension and truncation autovec patterns
RISC-V: Add conditional sign/zero extension and truncation autovec patterns
- - - -
-
-
-
2023-08-23
Lehua Ding
New
[V2] RISC-V: Add conditional unary neg/abs/not autovec patterns
[V2] RISC-V: Add conditional unary neg/abs/not autovec patterns
- - - -
-
-
-
2023-08-23
Lehua Ding
New
RISC-V: Add conditional unary neg/abs/not autovec patterns
RISC-V: Add conditional unary neg/abs/not autovec patterns
- - - -
-
-
-
2023-08-22
Lehua Ding
New
RISC-V: Change fnms testcases assertion to xfail
RISC-V: Change fnms testcases assertion to xfail
- - - -
-
-
-
2023-08-22
Lehua Ding
New
RISC-V: Fix -march error of zhinxmin testcases
RISC-V: Fix -march error of zhinxmin testcases
- - - -
-
-
-
2023-08-18
Lehua Ding
New
[V2] RISC-V: Add the missed half floating-point mode patterns of local_pic_load/store when only use…
[V2] RISC-V: Add the missed half floating-point mode patterns of local_pic_load/store when only use…
- - - -
-
-
-
2023-08-17
Lehua Ding
New
[V2] RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl
[V2] RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl
- - - -
-
-
-
2023-08-17
Lehua Ding
New
RISC-V: Fix XPASS slp testcases
RISC-V: Fix XPASS slp testcases
- - - -
-
-
-
2023-08-17
Lehua Ding
New
RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl
RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl
- - - -
-
-
-
2023-08-17
Lehua Ding
New
RISC-V: Add the missed half floating-point mode patterns of local_pic_load/store when only use zfhm…
RISC-V: Add the missed half floating-point mode patterns of local_pic_load/store when only use zfhm…
- - - -
-
-
-
2023-08-12
Lehua Ding
New
RISC-V: Revert the convert from vmv.s.x to vmv.v.i
RISC-V: Revert the convert from vmv.s.x to vmv.v.i
- - - -
-
-
-
2023-08-11
Lehua Ding
New
[V2] RISC-V: Fix error combine of pred_mov pattern
[V2] RISC-V: Fix error combine of pred_mov pattern
- - - -
-
-
-
2023-08-10
Lehua Ding
New
[V2,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function
RISC-V: Add an experimental vector calling convention
- - - -
-
-
-
2023-08-10
Lehua Ding
New
[V2,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed
RISC-V: Add an experimental vector calling convention
- - - -
-
-
-
2023-08-10
Lehua Ding
New
[V2,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns
RISC-V: Add an experimental vector calling convention
- - - -
-
-
-
2023-08-10
Lehua Ding
New
RISC-V: Fix error combine of pred_mov pattern
RISC-V: Fix error combine of pred_mov pattern
- - - -
-
-
-
2023-08-08
Lehua Ding
New
[V5] VECT: Support floating-point in-order reduction for length loop control
[V5] VECT: Support floating-point in-order reduction for length loop control
- - - -
-
-
-
2023-07-23
Lehua Ding
New
[3/3] RISC-V: Part-3: Output .variant_cc directive for vector function
RISC-V: Add an experimental vector calling convention
- - - -
-
-
-
2023-07-20
Lehua Ding
New
[2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed
RISC-V: Add an experimental vector calling convention
- - - -
-
-
-
2023-07-20
Lehua Ding
New
[1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns
RISC-V: Add an experimental vector calling convention
- - - -
-
-
-
2023-07-20
Lehua Ding
New
mklog: fix bugs of --append option
mklog: fix bugs of --append option
- - - -
-
-
-
2023-07-19
Lehua Ding
New
RISC-V: Fix testcase failed when default -mcmodel=medany
RISC-V: Fix testcase failed when default -mcmodel=medany
- - - -
-
-
-
2023-07-18
Lehua Ding
New
RISC-V: Remove testcase that cannot be compiled because VLEN limitation
RISC-V: Remove testcase that cannot be compiled because VLEN limitation
- - - -
-
-
-
2023-07-18
Lehua Ding
New
RISC-V: Ensure all implied extensions are included[PR110696]
RISC-V: Ensure all implied extensions are included[PR110696]
- - - -
-
-
-
2023-07-17
Lehua Ding
New
[V2] RISC-V: Throw compilation error for unknown sub-extension or supervisor extension
[V2] RISC-V: Throw compilation error for unknown sub-extension or supervisor extension
- - - -
-
-
-
2023-07-13
Lehua Ding
New
mklog: Add --append option to auto add generate ChangeLog to patch file
mklog: Add --append option to auto add generate ChangeLog to patch file
- - - -
-
-
-
2023-07-12
Lehua Ding
New
RISC-V: Throw compilation error for unknown sub-extension or supervisor extension
RISC-V: Throw compilation error for unknown sub-extension or supervisor extension
- - - -
-
-
-
2023-07-12
Lehua Ding
New
RISC-V: Add an experimental vector calling convention
RISC-V: Add an experimental vector calling convention
- - - -
-
-
-
2023-06-25
Lehua Ding
New
[committed] MAINTAINERS: Add myself to write after approval
[committed] MAINTAINERS: Add myself to write after approval
- - - -
-
-
-
2023-06-25
Lehua Ding
New
RISC-V: Fix compiler warning of riscv_arg_has_vector
RISC-V: Fix compiler warning of riscv_arg_has_vector
- - - -
-
-
-
2023-06-20
Lehua Ding
New
RISC-V: Add tuple vector mode psABI checking and simplify code
RISC-V: Add tuple vector mode psABI checking and simplify code
- - - -
-
-
-
2023-06-18
Lehua Ding
New
[V2] RISC-V: Ensure vector args and return use function stack to pass [PR110119]
[V2] RISC-V: Ensure vector args and return use function stack to pass [PR110119]
- - - -
-
-
-
2023-06-14
Lehua Ding
New
RISC-V: Ensure vector args and return use function stack to pass [PR110119]
RISC-V: Ensure vector args and return use function stack to pass [PR110119]
- - - -
-
-
-
2023-06-14
Lehua Ding
New
RISC-V: Fix PR 110119
RISC-V: Fix PR 110119
- - - -
-
-
-
2023-06-14
Lehua Ding
New
[V2] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"`
[V2] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"`
- - - -
-
-
-
2023-06-13
Lehua Ding
New
RISC-V: Remove duplicate `#include "riscv-vector-switch.def"`
RISC-V: Remove duplicate `#include "riscv-vector-switch.def"`
- - - -
-
-
-
2023-06-13
Lehua Ding
New
testsuite: fix the condition bug in tsvc s176
testsuite: fix the condition bug in tsvc s176
- - - -
-
-
-
2023-06-08
Lehua Ding
New
Add more ForEachMacros to clang-format file
Add more ForEachMacros to clang-format file
- - - -
-
-
-
2023-06-02
Lehua Ding
New
[V2,1/1,fwprop] : Add the support of forwarding the vec_duplicate rtx
[V2,1/1,fwprop] : Add the support of forwarding the vec_duplicate rtx
- - - -
-
-
-
2023-01-29
Lehua Ding
New
[1/1,fwprop] : Add the support of forwarding the vec_duplicate rtx
[1/1,fwprop] : Add the support of forwarding the vec_duplicate rtx
- - - -
-
-
-
2023-01-13
Lehua Ding
New
[1/1,fwprop] : Add the support of forwarding the vec_duplicate rtx
[1/1,fwprop] : Add the support of forwarding the vec_duplicate rtx
- - - -
-
-
-
2023-01-13
Lehua Ding
New
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