Show patches with: Submitter = Lehua Ding       |    State = Action Required       |    Archived = No       |   146 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[1/1,fwprop] : Add the support of forwarding the vec_duplicate rtx [1/1,fwprop] : Add the support of forwarding the vec_duplicate rtx - - - - --- 2023-01-13 Lehua Ding New
[1/1,fwprop] : Add the support of forwarding the vec_duplicate rtx [1/1,fwprop] : Add the support of forwarding the vec_duplicate rtx - - - - --- 2023-01-13 Lehua Ding New
[V2,1/1,fwprop] : Add the support of forwarding the vec_duplicate rtx [V2,1/1,fwprop] : Add the support of forwarding the vec_duplicate rtx - - - - --- 2023-01-29 Lehua Ding New
Add more ForEachMacros to clang-format file Add more ForEachMacros to clang-format file - - - - --- 2023-06-02 Lehua Ding New
testsuite: fix the condition bug in tsvc s176 testsuite: fix the condition bug in tsvc s176 - - - - --- 2023-06-08 Lehua Ding New
RISC-V: Remove duplicate `#include "riscv-vector-switch.def"` RISC-V: Remove duplicate `#include "riscv-vector-switch.def"` - - - - --- 2023-06-13 Lehua Ding New
[V2] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"` [V2] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"` - - - - --- 2023-06-13 Lehua Ding New
RISC-V: Fix PR 110119 RISC-V: Fix PR 110119 - - - - --- 2023-06-14 Lehua Ding New
RISC-V: Ensure vector args and return use function stack to pass [PR110119] RISC-V: Ensure vector args and return use function stack to pass [PR110119] - - - - --- 2023-06-14 Lehua Ding New
[V2] RISC-V: Ensure vector args and return use function stack to pass [PR110119] [V2] RISC-V: Ensure vector args and return use function stack to pass [PR110119] - - - - --- 2023-06-14 Lehua Ding New
RISC-V: Add tuple vector mode psABI checking and simplify code RISC-V: Add tuple vector mode psABI checking and simplify code - - - - --- 2023-06-18 Lehua Ding New
RISC-V: Fix compiler warning of riscv_arg_has_vector RISC-V: Fix compiler warning of riscv_arg_has_vector - - - - --- 2023-06-20 Lehua Ding New
[committed] MAINTAINERS: Add myself to write after approval [committed] MAINTAINERS: Add myself to write after approval - - - - --- 2023-06-25 Lehua Ding New
RISC-V: Add an experimental vector calling convention RISC-V: Add an experimental vector calling convention - - - - --- 2023-06-25 Lehua Ding New
RISC-V: Throw compilation error for unknown sub-extension or supervisor extension RISC-V: Throw compilation error for unknown sub-extension or supervisor extension - - - - --- 2023-07-12 Lehua Ding New
mklog: Add --append option to auto add generate ChangeLog to patch file mklog: Add --append option to auto add generate ChangeLog to patch file - - - - --- 2023-07-12 Lehua Ding New
[V2] RISC-V: Throw compilation error for unknown sub-extension or supervisor extension [V2] RISC-V: Throw compilation error for unknown sub-extension or supervisor extension - - - - --- 2023-07-13 Lehua Ding New
RISC-V: Ensure all implied extensions are included[PR110696] RISC-V: Ensure all implied extensions are included[PR110696] - - - - --- 2023-07-17 Lehua Ding New
RISC-V: Remove testcase that cannot be compiled because VLEN limitation RISC-V: Remove testcase that cannot be compiled because VLEN limitation - - - - --- 2023-07-18 Lehua Ding New
RISC-V: Fix testcase failed when default -mcmodel=medany RISC-V: Fix testcase failed when default -mcmodel=medany - - - - --- 2023-07-18 Lehua Ding New
mklog: fix bugs of --append option mklog: fix bugs of --append option - - - - --- 2023-07-19 Lehua Ding New
[1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns RISC-V: Add an experimental vector calling convention - - - - --- 2023-07-20 Lehua Ding New
[2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed RISC-V: Add an experimental vector calling convention - - - - --- 2023-07-20 Lehua Ding New
[3/3] RISC-V: Part-3: Output .variant_cc directive for vector function RISC-V: Add an experimental vector calling convention - - - - --- 2023-07-20 Lehua Ding New
[V5] VECT: Support floating-point in-order reduction for length loop control [V5] VECT: Support floating-point in-order reduction for length loop control - - - - --- 2023-07-23 Lehua Ding New
RISC-V: Fix error combine of pred_mov pattern RISC-V: Fix error combine of pred_mov pattern - - - - --- 2023-08-08 Lehua Ding New
[V2,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns RISC-V: Add an experimental vector calling convention - - - - --- 2023-08-10 Lehua Ding New
[V2,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed RISC-V: Add an experimental vector calling convention - - - - --- 2023-08-10 Lehua Ding New
[V2,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function RISC-V: Add an experimental vector calling convention - - - - --- 2023-08-10 Lehua Ding New
[V2] RISC-V: Fix error combine of pred_mov pattern [V2] RISC-V: Fix error combine of pred_mov pattern - - - - --- 2023-08-10 Lehua Ding New
RISC-V: Revert the convert from vmv.s.x to vmv.v.i RISC-V: Revert the convert from vmv.s.x to vmv.v.i - - - - --- 2023-08-11 Lehua Ding New
RISC-V: Add the missed half floating-point mode patterns of local_pic_load/store when only use zfhm… RISC-V: Add the missed half floating-point mode patterns of local_pic_load/store when only use zfhm… - - - - --- 2023-08-12 Lehua Ding New
RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl - - - - --- 2023-08-17 Lehua Ding New
RISC-V: Fix XPASS slp testcases RISC-V: Fix XPASS slp testcases - - - - --- 2023-08-17 Lehua Ding New
[V2] RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl [V2] RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl - - - - --- 2023-08-17 Lehua Ding New
[V2] RISC-V: Add the missed half floating-point mode patterns of local_pic_load/store when only use… [V2] RISC-V: Add the missed half floating-point mode patterns of local_pic_load/store when only use… - - - - --- 2023-08-17 Lehua Ding New
RISC-V: Fix -march error of zhinxmin testcases RISC-V: Fix -march error of zhinxmin testcases - - - - --- 2023-08-18 Lehua Ding New
RISC-V: Change fnms testcases assertion to xfail RISC-V: Change fnms testcases assertion to xfail - - - - --- 2023-08-22 Lehua Ding New
RISC-V: Add conditional unary neg/abs/not autovec patterns RISC-V: Add conditional unary neg/abs/not autovec patterns - - - - --- 2023-08-22 Lehua Ding New
[V2] RISC-V: Add conditional unary neg/abs/not autovec patterns [V2] RISC-V: Add conditional unary neg/abs/not autovec patterns - - - - --- 2023-08-23 Lehua Ding New
RISC-V: Add conditional sign/zero extension and truncation autovec patterns RISC-V: Add conditional sign/zero extension and truncation autovec patterns - - - - --- 2023-08-23 Lehua Ding New
RISC-V: Add conditional convert autovec patterns between FPs RISC-V: Add conditional convert autovec patterns between FPs - - - - --- 2023-08-23 Lehua Ding New
RISC-V: Add conditional autovec convert(INT<->FP) patterns RISC-V: Add conditional autovec convert(INT<->FP) patterns - - - - --- 2023-08-24 Lehua Ding New
[V2] RISC-V: Add conditional autovec convert(INT<->INT) patterns [V2] RISC-V: Add conditional autovec convert(INT<->INT) patterns - - - - --- 2023-08-25 Lehua Ding New
RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} - - - - --- 2023-08-25 Lehua Ding New
[COMMITTED,V3] RISC-V: Fix error combine of pred_mov pattern [COMMITTED,V3] RISC-V: Fix error combine of pred_mov pattern - - - - --- 2023-08-29 Lehua Ding New
[V2] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} [V2] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} - - - - --- 2023-08-29 Lehua Ding New
[V3] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} [V3] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} - - - - --- 2023-08-29 Lehua Ding New
[V3,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns RISC-V: Add an experimental vector calling convention - - - - --- 2023-08-30 Lehua Ding New
[V3,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed RISC-V: Add an experimental vector calling convention - - - - --- 2023-08-30 Lehua Ding New
[V3,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function RISC-V: Add an experimental vector calling convention - - - - --- 2023-08-30 Lehua Ding New
RISC-V: Fix vsetvl pass ICE RISC-V: Fix vsetvl pass ICE - - - - --- 2023-08-30 Lehua Ding New
RISC-V: Refactor and clean emit_{vlmax, nonvlmax}_xxx functions RISC-V: Refactor and clean emit_{vlmax, nonvlmax}_xxx functions - - - - --- 2023-08-30 Lehua Ding New
RISC-V: Change vsetvl tail and mask policy to default policy RISC-V: Change vsetvl tail and mask policy to default policy - - - - --- 2023-08-31 Lehua Ding New
[V4,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns RISC-V: Add an experimental vector calling convention - - - - --- 2023-08-31 Lehua Ding New
[V4,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed RISC-V: Add an experimental vector calling convention - - - - --- 2023-08-31 Lehua Ding New
[V4,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function RISC-V: Add an experimental vector calling convention - - - - --- 2023-08-31 Lehua Ding New
[1/4] RISC-V: Adjust expand_cond_len_{unary,binop,op} api Add conditional autovec convert patterns - - - - --- 2023-09-01 Lehua Ding New
[2/4] RISC-V: Add conditional autovec convert(INT<->INT) patterns Add conditional autovec convert patterns - - - - --- 2023-09-01 Lehua Ding New
[3/4] RISC-V: Add conditional autovec convert(FP<->FP) patterns Add conditional autovec convert patterns - - - - --- 2023-09-01 Lehua Ding New
[4/4] RISC-V: Add conditional autovec convert(INT<->FP) patterns Add conditional autovec convert patterns - - - - --- 2023-09-01 Lehua Ding New
RISC-V: Add conditional sqrt autovec pattern RISC-V: Add conditional sqrt autovec pattern - - - - --- 2023-09-04 Lehua Ding New
RISC-V: Keep vlmax vector operators in simple form until split1 pass RISC-V: Keep vlmax vector operators in simple form until split1 pass - - - - --- 2023-09-04 Lehua Ding New
[V5,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns RISC-V: Add an experimental vector calling convention - - - - --- 2023-09-05 Lehua Ding New
[V5,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed RISC-V: Add an experimental vector calling convention - - - - --- 2023-09-05 Lehua Ding New
[V5,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function RISC-V: Add an experimental vector calling convention - - - - --- 2023-09-05 Lehua Ding New
Support folding min(poly,poly) to const Support folding min(poly,poly) to const - - - - --- 2023-09-08 Lehua Ding New
[V2] Support folding min(poly,poly) to const [V2] Support folding min(poly,poly) to const - - - - --- 2023-09-08 Lehua Ding New
[V3] Support folding min(poly,poly) to const [V3] Support folding min(poly,poly) to const - - - - --- 2023-09-08 Lehua Ding New
RISC-V: Add missed cond autovec testcases RISC-V: Add missed cond autovec testcases - - - - --- 2023-09-12 Lehua Ding New
RISC-V: Support cond vfsgnj.vv autovec pattern RISC-V: Support cond vfsgnj.vv autovec pattern - - - - --- 2023-09-12 Lehua Ding New
RISC-V: Support cond vnsrl/vnsra RISC-V: Support cond vnsrl/vnsra - - - - --- 2023-09-12 Lehua Ding New
RISC-V: Support cond vmulh.vv and vmulu.vv RISC-V: Support cond vmulh.vv and vmulu.vv - - - - --- 2023-09-12 Lehua Ding New
[1/2] RISC-V: Cleanup redundant reduction patterns after refactor vector mode [1/2] RISC-V: Cleanup redundant reduction patterns after refactor vector mode - - - - --- 2023-09-13 Lehua Ding New
[2/2] RISC-V: Refactor vector reduction patterns [1/2] RISC-V: Cleanup redundant reduction patterns after refactor vector mode - - - - --- 2023-09-13 Lehua Ding New
RISC-V: Support combine extend and reduce sum to widen reduce sum RISC-V: Support combine extend and reduce sum to widen reduce sum - - - - --- 2023-09-14 Lehua Ding New
RISC-V: Refactor expand_reduction and cleanup enum reduction_type RISC-V: Refactor expand_reduction and cleanup enum reduction_type - - - - --- 2023-09-15 Lehua Ding New
RISC-V: Fix using wrong mode to get reduction insn vlmax RISC-V: Fix using wrong mode to get reduction insn vlmax - - - - --- 2023-09-15 Lehua Ding New
RISC-V: Refactor and cleanup fma patterns RISC-V: Refactor and cleanup fma patterns - - - - --- 2023-09-18 Lehua Ding New
RISC-V: Add fixed PR111255 testcase by other patch RISC-V: Add fixed PR111255 testcase by other patch - - - - --- 2023-09-18 Lehua Ding New
RISC-V: Removed misleading comments in testcases RISC-V: Removed misleading comments in testcases - - - - --- 2023-09-18 Lehua Ding New
RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum - - - - --- 2023-09-18 Lehua Ding New
RISC-V: Fixed ICE caused by missing operand RISC-V: Fixed ICE caused by missing operand - - - - --- 2023-09-20 Lehua Ding New
RISC-V: Reorganize and rename combine patterns in autovec-opt.md RISC-V: Reorganize and rename combine patterns in autovec-opt.md - - - - --- 2023-09-20 Lehua Ding New
[V2] RISC-V: Support combine cond extend and reduce sum to widen reduce sum [V2] RISC-V: Support combine cond extend and reduce sum to widen reduce sum - - - - --- 2023-09-20 Lehua Ding New
[1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op [1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op - - - - --- 2023-09-20 Lehua Ding New
[2/2] RISC-V: Add assert of the number of vmerge in autovec cond testcases [1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op - - - - --- 2023-09-20 Lehua Ding New
RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names - - - - --- 2023-09-21 Lehua Ding New
[V3] RISC-V: Support combine cond extend and reduce sum to widen reduce sum [V3] RISC-V: Support combine cond extend and reduce sum to widen reduce sum - - - - --- 2023-09-21 Lehua Ding New
RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functi… RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functi… - - - - --- 2023-09-21 Lehua Ding New
[V2] RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn f… [V2] RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn f… - - - - --- 2023-09-21 Lehua Ding New
[COMMITTED] RISC-V: Split VLS avl_type from NONVLMAX avl_type [COMMITTED] RISC-V: Split VLS avl_type from NONVLMAX avl_type - - - - --- 2023-09-22 Lehua Ding New
[COMMITTED,V4] RISC-V: Support combine cond extend and reduce sum to widen reduce sum [COMMITTED,V4] RISC-V: Support combine cond extend and reduce sum to widen reduce sum - - - - --- 2023-09-22 Lehua Ding New
RISC-V: Refactor and cleanup vsetvl pass RISC-V: Refactor and cleanup vsetvl pass - - - - --- 2023-10-16 Lehua Ding New
RISC-V: Fix failed testcase when use -cmodel=medany RISC-V: Fix failed testcase when use -cmodel=medany - - - - --- 2023-10-17 Lehua Ding New
[V2,01/14] RISC-V: P1: Refactor avl_info/vl_vtype_info/vector_insn_info Refactor and cleanup vsetvl pass - - - - --- 2023-10-17 Lehua Ding New
[V2,02/14] RISC-V: P2: Refactor and cleanup demand system Refactor and cleanup vsetvl pass - - - - --- 2023-10-17 Lehua Ding New
[V2,03/14] RISC-V: P3: Refactor vector_infos_manager Refactor and cleanup vsetvl pass - - - - --- 2023-10-17 Lehua Ding New
[V2,04/14] RISC-V: P4: move method from pass_vsetvl to pre_vsetvl Refactor and cleanup vsetvl pass - - - - --- 2023-10-17 Lehua Ding New
[V2,05/14] RISC-V: P5: combine phase 1 and 2 Refactor and cleanup vsetvl pass - - - - --- 2023-10-17 Lehua Ding New
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