diff mbox series

[V2] RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl

Message ID 20230817122923.3114045-1-lehua.ding@rivai.ai
State New
Headers show
Series [V2] RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl | expand

Commit Message

Lehua Ding Aug. 17, 2023, 12:29 p.m. UTC 
Hi,

This little patch fix the fail testcase
(gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c)
after apply this patch
(https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627121.html).
The specific reason is that the vsetvl pass has bug and this patch
forbidden the fuse of this case. This patch needs to be committed
before that patch to work.

Best,
Lehua

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (pass_vsetvl::backward_demand_fusion):
	  Forbidden.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c:
	  Address failure due to uninitialized vtype register.
---
 gcc/config/riscv/riscv-vsetvl.cc                | 17 +++++++++++++++++
 .../autovec/gather-scatter/strided_load_run-1.c |  6 ++++++
 2 files changed, 23 insertions(+)

Comments

Robin Dapp Aug. 17, 2023, 2:10 p.m. UTC | #1 
OK, thanks.

Regards
 Robin
Lehua Ding Aug. 18, 2023, 3 a.m. UTC | #2 
Committed, thanks Robin.




------------------ Original ------------------
From:                                                                                                                        "Robin Dapp"                                                                                    <rdapp.gcc@gmail.com&gt;;
Date:&nbsp;Thu, Aug 17, 2023 10:10 PM
To:&nbsp;"Lehua Ding"<lehua.ding@rivai.ai&gt;;"gcc-patches"<gcc-patches@gcc.gnu.org&gt;;
Cc:&nbsp;"rdapp.gcc"<rdapp.gcc@gmail.com&gt;;"juzhe.zhong"<juzhe.zhong@rivai.ai&gt;;"kito.cheng"<kito.cheng@gmail.com&gt;;"palmer"<palmer@rivosinc.com&gt;;"jeffreyalaw"<jeffreyalaw@gmail.com&gt;;
Subject:&nbsp;Re: [PATCH V2] RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl



OK, thanks.

Regards
Robin
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 79cbac01047..2d8fa754ea0 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -3330,6 +3330,23 @@  pass_vsetvl::backward_demand_fusion (void)
 	  else if (block_info.reaching_out.dirty_p ())
 	    {
 	      /* DIRTY -> DIRTY or VALID -> DIRTY.  */
+
+	      /* Forbidden this case fuse because it change the value of a5.
+		   bb 1: vsetvl zero, no_zero_avl
+			 ...
+			 use a5
+			 ...
+		   bb 2: vsetvl a5, zero
+		 =>
+		   bb 1: vsetvl a5, zero
+			 ...
+			 use a5
+			 ...
+		   bb 2:
+	      */
+	      if (block_info.reaching_out.demand_p (DEMAND_NONZERO_AVL)
+		  && vlmax_avl_p (prop.get_avl ()))
+		continue;
 	      vector_insn_info new_info;
 
 	      if (block_info.reaching_out.compatible_p (prop))
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c
index 7ffa93bf13f..7eeb22aade2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c
@@ -7,6 +7,12 @@ 
 int
 main (void)
 {
+  /* FIXME: The purpose of this assembly is to ensure that the vtype register is
+     initialized befor instructions such as vmv1r.v are executed. Otherwise you
+     will get illegal instruction errors when running with spike+pk. This is an
+     interim solution for reduce unnecessary failures and a unified solution
+     will come later. */
+  asm volatile("vsetivli x0, 0, e8, m1, ta, ma");
 #define RUN_LOOP(DATA_TYPE, BITS)                                              \
   DATA_TYPE dest_##DATA_TYPE##_##BITS[(BITS - 3) * (BITS + 13)];               \
   DATA_TYPE dest2_##DATA_TYPE##_##BITS[(BITS - 3) * (BITS + 13)];              \