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: Submitter =
Lehua Ding
| State =
Action Required
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| 146 patches
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prom
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Jaehoon
jacmet
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xypron
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hegdevasant
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metan
bmeng
jagan
ukleinek
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kevery
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rw
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pablo
pablo
wbx
Hauke
Hauke
legoater
legoater
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chleroy
svanheule
bjonglez
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aik
sbabic
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pevik
xback
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Andes
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Apply
«
1
2
»
Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[4/4] lra: Apply DF_LIVE_SUBREG data
Add DF_LIVE_SUBREG data and apply to IRA and LRA
- - - -
-
-
-
2024-04-24
Lehua Ding
New
[3/4] ira: Apply DF_LIVE_SUBREG data
Add DF_LIVE_SUBREG data and apply to IRA and LRA
- - - -
-
-
-
2024-04-24
Lehua Ding
New
[2/4] df: Add DF_LIVE_SUBREG problem
Add DF_LIVE_SUBREG data and apply to IRA and LRA
- - - -
-
-
-
2024-04-24
Lehua Ding
New
[1/4] df: Add -ftrack-subreg-liveness option
Add DF_LIVE_SUBREG data and apply to IRA and LRA
- - - -
-
-
-
2024-04-24
Lehua Ding
New
[4/4] lra: Apply DF_LIVE_SUBREG data
Add DF_LIVE_SUBREG data and apply to IRA and LRA
- - - -
-
-
-
2024-02-03
Lehua Ding
New
[3/4] ira: Apply DF_LIVE_SUBREG data
Add DF_LIVE_SUBREG data and apply to IRA and LRA
- - - -
-
-
-
2024-02-03
Lehua Ding
New
[2/4] df: Add DF_LIVE_SUBREG problem
Add DF_LIVE_SUBREG data and apply to IRA and LRA
- - - -
-
-
-
2024-02-03
Lehua Ding
New
[1/4] df: Add -ftrack-subreg-liveness option
Add DF_LIVE_SUBREG data and apply to IRA and LRA
- - - -
-
-
-
2024-02-03
Lehua Ding
New
x86: Make testcase apx-spill_to_egprs-1.c more robust
x86: Make testcase apx-spill_to_egprs-1.c more robust
- - - -
-
-
-
2023-11-14
Lehua Ding
New
[V3,7/7] lra: Support subreg live range track and conflict detect
ira/lra: Support subreg coalesce
- - - -
-
-
-
2023-11-12
Lehua Ding
New
[V3,6/7] lra: Switch to live_subreg data flow
ira/lra: Support subreg coalesce
- - - -
-
-
-
2023-11-12
Lehua Ding
New
[V3,5/7] ira: Add all nregs >= 2 pseudos to tracke subreg list
ira/lra: Support subreg coalesce
- - - -
-
-
-
2023-11-12
Lehua Ding
New
[V3,4/7] ira: Support subreg copy
ira/lra: Support subreg coalesce
- - - -
-
-
-
2023-11-12
Lehua Ding
New
[V3,3/7] ira: Support subreg live range track
ira/lra: Support subreg coalesce
- - - -
-
-
-
2023-11-12
Lehua Ding
New
[V3,2/7] ira: Switch to live_subreg data
ira/lra: Support subreg coalesce
- - - -
-
-
-
2023-11-12
Lehua Ding
New
[V3,1/7] df: Add DF_LIVE_SUBREG problem
ira/lra: Support subreg coalesce
- - - -
-
-
-
2023-11-12
Lehua Ding
New
RISC-V: Removed unnecessary sign-extend for vsetvl
RISC-V: Removed unnecessary sign-extend for vsetvl
- - - -
-
-
-
2023-11-08
Lehua Ding
New
[7/7] lra: Support subreg live range track and conflict detect
ira/lra: Support subreg coalesce
- - - -
-
-
-
2023-11-08
Lehua Ding
New
[6/7] lra: Apply live_subreg df_problem to lra pass
ira/lra: Support subreg coalesce
- - - -
-
-
-
2023-11-08
Lehua Ding
New
[5/7] ira: Add all nregs >= 2 pseudos to tracke subreg list
ira/lra: Support subreg coalesce
- - - -
-
-
-
2023-11-08
Lehua Ding
New
[4/7] ira: Support subreg copy
ira/lra: Support subreg coalesce
- - - -
-
-
-
2023-11-08
Lehua Ding
New
[3/7] ira: Support subreg live range track
ira/lra: Support subreg coalesce
- - - -
-
-
-
2023-11-08
Lehua Ding
New
[2/7] ira: Add live_subreg problem and apply to ira pass
ira/lra: Support subreg coalesce
- - - -
-
-
-
2023-11-08
Lehua Ding
New
[1/7] ira: Refactor the handling of register conflicts to make it more general
ira/lra: Support subreg coalesce
- - - -
-
-
-
2023-11-08
Lehua Ding
New
RISC-V: Fixed failed rvv combine testcases
RISC-V: Fixed failed rvv combine testcases
- - - -
-
-
-
2023-11-07
Lehua Ding
New
RISC-V: Add the missed combine of [u]int64 -> _Float16 and vcond
RISC-V: Add the missed combine of [u]int64 -> _Float16 and vcond
- - - -
-
-
-
2023-10-31
Lehua Ding
New
[V3,11/11] RISC-V: P11: Adjust and add testcases
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-19
Lehua Ding
New
[V3,10/11] RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-19
Lehua Ding
New
[V3,09/11] RISC-V: P9: Cleanup and reorganize helper functions
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-19
Lehua Ding
New
[V3,08/11] RISC-V: P8: Refactor emit-vsetvl phase and delete post optimization
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-19
Lehua Ding
New
[V3,07/11] RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-19
Lehua Ding
New
[V3,06/11] RISC-V: P6: Add computing reaching definition data flow
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-19
Lehua Ding
New
[V3,05/11] RISC-V: P5: Combine phase 1 and 2
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-19
Lehua Ding
New
[V3,04/11] RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-19
Lehua Ding
New
[V3,03/11] RISC-V: P3: Refactor vector_infos_manager
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-19
Lehua Ding
New
[V3,02/11] RISC-V: P2: Refactor and cleanup demand system
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-19
Lehua Ding
New
[V3,01/11] RISC-V: P1: Refactor avl_info/vl_vtype_info/vector_insn_info/vector_block_info
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-19
Lehua Ding
New
[V2,14/14] RISC-V: P14: Adjust and add testcases
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-17
Lehua Ding
New
[V2,13/14] RISC-V: P13: Reorganize functions used to modify RTL
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-17
Lehua Ding
New
[V2,12/14] RISC-V: P12: Delete riscv-vsetvl.h
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-17
Lehua Ding
New
[V2,11/14] RISC-V: P11: Adjust vector_block_info to vsetvl_block_info class
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-17
Lehua Ding
New
[V2,10/14] RISC-V: P10: Cleanup helper functions
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-17
Lehua Ding
New
[V2,09/14] RISC-V: P9: Cleanup post optimize phase
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-17
Lehua Ding
New
[V2,08/14] RISC-V: P8: Unified insert and delete of vsetvl insn into Phase 4
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-17
Lehua Ding
New
[V2,07/14] RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-17
Lehua Ding
New
[V2,06/14] RISC-V: P6: Add computing reaching definition data flow
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-17
Lehua Ding
New
[V2,05/14] RISC-V: P5: combine phase 1 and 2
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-17
Lehua Ding
New
[V2,04/14] RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-17
Lehua Ding
New
[V2,03/14] RISC-V: P3: Refactor vector_infos_manager
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-17
Lehua Ding
New
[V2,02/14] RISC-V: P2: Refactor and cleanup demand system
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-17
Lehua Ding
New
[V2,01/14] RISC-V: P1: Refactor avl_info/vl_vtype_info/vector_insn_info
Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-17
Lehua Ding
New
RISC-V: Fix failed testcase when use -cmodel=medany
RISC-V: Fix failed testcase when use -cmodel=medany
- - - -
-
-
-
2023-10-17
Lehua Ding
New
RISC-V: Refactor and cleanup vsetvl pass
RISC-V: Refactor and cleanup vsetvl pass
- - - -
-
-
-
2023-10-16
Lehua Ding
New
[COMMITTED,V4] RISC-V: Support combine cond extend and reduce sum to widen reduce sum
[COMMITTED,V4] RISC-V: Support combine cond extend and reduce sum to widen reduce sum
- - - -
-
-
-
2023-09-22
Lehua Ding
New
[COMMITTED] RISC-V: Split VLS avl_type from NONVLMAX avl_type
[COMMITTED] RISC-V: Split VLS avl_type from NONVLMAX avl_type
- - - -
-
-
-
2023-09-22
Lehua Ding
New
[V2] RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn f…
[V2] RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn f…
- - - -
-
-
-
2023-09-21
Lehua Ding
New
RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functi…
RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functi…
- - - -
-
-
-
2023-09-21
Lehua Ding
New
[V3] RISC-V: Support combine cond extend and reduce sum to widen reduce sum
[V3] RISC-V: Support combine cond extend and reduce sum to widen reduce sum
- - - -
-
-
-
2023-09-21
Lehua Ding
New
RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names
RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names
- - - -
-
-
-
2023-09-21
Lehua Ding
New
[2/2] RISC-V: Add assert of the number of vmerge in autovec cond testcases
[1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op
- - - -
-
-
-
2023-09-20
Lehua Ding
New
[1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op
[1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op
- - - -
-
-
-
2023-09-20
Lehua Ding
New
[V2] RISC-V: Support combine cond extend and reduce sum to widen reduce sum
[V2] RISC-V: Support combine cond extend and reduce sum to widen reduce sum
- - - -
-
-
-
2023-09-20
Lehua Ding
New
RISC-V: Reorganize and rename combine patterns in autovec-opt.md
RISC-V: Reorganize and rename combine patterns in autovec-opt.md
- - - -
-
-
-
2023-09-20
Lehua Ding
New
RISC-V: Fixed ICE caused by missing operand
RISC-V: Fixed ICE caused by missing operand
- - - -
-
-
-
2023-09-20
Lehua Ding
New
RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum
RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum
- - - -
-
-
-
2023-09-18
Lehua Ding
New
RISC-V: Removed misleading comments in testcases
RISC-V: Removed misleading comments in testcases
- - - -
-
-
-
2023-09-18
Lehua Ding
New
RISC-V: Add fixed PR111255 testcase by other patch
RISC-V: Add fixed PR111255 testcase by other patch
- - - -
-
-
-
2023-09-18
Lehua Ding
New
RISC-V: Refactor and cleanup fma patterns
RISC-V: Refactor and cleanup fma patterns
- - - -
-
-
-
2023-09-18
Lehua Ding
New
RISC-V: Fix using wrong mode to get reduction insn vlmax
RISC-V: Fix using wrong mode to get reduction insn vlmax
- - - -
-
-
-
2023-09-15
Lehua Ding
New
RISC-V: Refactor expand_reduction and cleanup enum reduction_type
RISC-V: Refactor expand_reduction and cleanup enum reduction_type
- - - -
-
-
-
2023-09-15
Lehua Ding
New
RISC-V: Support combine extend and reduce sum to widen reduce sum
RISC-V: Support combine extend and reduce sum to widen reduce sum
- - - -
-
-
-
2023-09-14
Lehua Ding
New
[2/2] RISC-V: Refactor vector reduction patterns
[1/2] RISC-V: Cleanup redundant reduction patterns after refactor vector mode
- - - -
-
-
-
2023-09-13
Lehua Ding
New
[1/2] RISC-V: Cleanup redundant reduction patterns after refactor vector mode
[1/2] RISC-V: Cleanup redundant reduction patterns after refactor vector mode
- - - -
-
-
-
2023-09-13
Lehua Ding
New
RISC-V: Support cond vmulh.vv and vmulu.vv
RISC-V: Support cond vmulh.vv and vmulu.vv
- - - -
-
-
-
2023-09-12
Lehua Ding
New
RISC-V: Support cond vnsrl/vnsra
RISC-V: Support cond vnsrl/vnsra
- - - -
-
-
-
2023-09-12
Lehua Ding
New
RISC-V: Support cond vfsgnj.vv autovec pattern
RISC-V: Support cond vfsgnj.vv autovec pattern
- - - -
-
-
-
2023-09-12
Lehua Ding
New
RISC-V: Add missed cond autovec testcases
RISC-V: Add missed cond autovec testcases
- - - -
-
-
-
2023-09-12
Lehua Ding
New
[V3] Support folding min(poly,poly) to const
[V3] Support folding min(poly,poly) to const
- - - -
-
-
-
2023-09-08
Lehua Ding
New
[V2] Support folding min(poly,poly) to const
[V2] Support folding min(poly,poly) to const
- - - -
-
-
-
2023-09-08
Lehua Ding
New
Support folding min(poly,poly) to const
Support folding min(poly,poly) to const
- - - -
-
-
-
2023-09-08
Lehua Ding
New
[V5,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function
RISC-V: Add an experimental vector calling convention
- - - -
-
-
-
2023-09-05
Lehua Ding
New
[V5,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed
RISC-V: Add an experimental vector calling convention
- - - -
-
-
-
2023-09-05
Lehua Ding
New
[V5,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns
RISC-V: Add an experimental vector calling convention
- - - -
-
-
-
2023-09-05
Lehua Ding
New
RISC-V: Keep vlmax vector operators in simple form until split1 pass
RISC-V: Keep vlmax vector operators in simple form until split1 pass
- - - -
-
-
-
2023-09-04
Lehua Ding
New
RISC-V: Add conditional sqrt autovec pattern
RISC-V: Add conditional sqrt autovec pattern
- - - -
-
-
-
2023-09-04
Lehua Ding
New
[4/4] RISC-V: Add conditional autovec convert(INT<->FP) patterns
Add conditional autovec convert patterns
- - - -
-
-
-
2023-09-01
Lehua Ding
New
[3/4] RISC-V: Add conditional autovec convert(FP<->FP) patterns
Add conditional autovec convert patterns
- - - -
-
-
-
2023-09-01
Lehua Ding
New
[2/4] RISC-V: Add conditional autovec convert(INT<->INT) patterns
Add conditional autovec convert patterns
- - - -
-
-
-
2023-09-01
Lehua Ding
New
[1/4] RISC-V: Adjust expand_cond_len_{unary,binop,op} api
Add conditional autovec convert patterns
- - - -
-
-
-
2023-09-01
Lehua Ding
New
[V4,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function
RISC-V: Add an experimental vector calling convention
- - - -
-
-
-
2023-08-31
Lehua Ding
New
[V4,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed
RISC-V: Add an experimental vector calling convention
- - - -
-
-
-
2023-08-31
Lehua Ding
New
[V4,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns
RISC-V: Add an experimental vector calling convention
- - - -
-
-
-
2023-08-31
Lehua Ding
New
RISC-V: Change vsetvl tail and mask policy to default policy
RISC-V: Change vsetvl tail and mask policy to default policy
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2023-08-31
Lehua Ding
New
RISC-V: Refactor and clean emit_{vlmax, nonvlmax}_xxx functions
RISC-V: Refactor and clean emit_{vlmax, nonvlmax}_xxx functions
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2023-08-30
Lehua Ding
New
RISC-V: Fix vsetvl pass ICE
RISC-V: Fix vsetvl pass ICE
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2023-08-30
Lehua Ding
New
[V3,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function
RISC-V: Add an experimental vector calling convention
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2023-08-30
Lehua Ding
New
[V3,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed
RISC-V: Add an experimental vector calling convention
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2023-08-30
Lehua Ding
New
[V3,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns
RISC-V: Add an experimental vector calling convention
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2023-08-30
Lehua Ding
New
[V3] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop}
[V3] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop}
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2023-08-29
Lehua Ding
New
[V2] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop}
[V2] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop}
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2023-08-29
Lehua Ding
New
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