diff mbox series

[v2,6/9] riscv: Change to use positive offset to access relocation entries

Message ID 20230413062008.981238-6-bmeng@tinylab.org
State Accepted
Commit 485f59307957269786384c30e4eee59716727f07
Delegated to: Andes
Headers show
Series [v2,1/9] riscv: Optimize source end address calculation in start.S | expand

Commit Message

Bin Meng April 13, 2023, 6:20 a.m. UTC 
The codes currently skip the very first relocation entry, and have
an inaccurate comment "skip first reserved entry" indicating that
the first entry is reserved, but later it references the elements
in the first relocation entry using a minus offset.

Change to use a positive offset so that there is no need to skip
the first relocation entry.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
---

(no changes since v1)

 arch/riscv/cpu/start.S | 19 +++++++------------
 1 file changed, 7 insertions(+), 12 deletions(-)

Comments

Leo Liang April 20, 2023, 7:46 a.m. UTC | #1 
On Thu, Apr 13, 2023 at 02:20:05PM +0800, Bin Meng wrote:
> The codes currently skip the very first relocation entry, and have
> an inaccurate comment "skip first reserved entry" indicating that
> the first entry is reserved, but later it references the elements
> in the first relocation entry using a minus offset.
> 
> Change to use a positive offset so that there is no need to skip
> the first relocation entry.
> 
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
> 
> (no changes since v1)
> 
>  arch/riscv/cpu/start.S | 19 +++++++------------
>  1 file changed, 7 insertions(+), 12 deletions(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff mbox series

Patch

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 879bdc1803..c09d1cb412 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -302,17 +302,12 @@  fix_rela_dyn:
 	add	t1, t1, t6		/* t1 <- rela_dyn_start in RAM */
 	add	t2, t2, t6		/* t2 <- rela_dyn_end in RAM */
 
-/*
- * skip first reserved entry: address, type, addend
- */
-	j	10f
-
 6:
-	LREG	t5, -(REGBYTES*2)(t1)	/* t5 <-- relocation info:type */
+	LREG	t5, REGBYTES(t1)	/* t5 <-- relocation info:type */
 	li	t3, R_RISCV_RELATIVE	/* reloc type R_RISCV_RELATIVE */
 	bne	t5, t3, 8f		/* skip non-RISCV_RELOC entries */
-	LREG	t3, -(REGBYTES*3)(t1)
-	LREG	t5, -(REGBYTES)(t1)	/* t5 <-- addend */
+	LREG	t3, 0(t1)
+	LREG	t5, (REGBYTES * 2)(t1)	/* t5 <-- addend */
 	add	t5, t5, t6		/* t5 <-- location to fix up in RAM */
 	add	t3, t3, t6		/* t3 <-- location to fix up in RAM */
 	SREG	t5, 0(t3)
@@ -328,19 +323,19 @@  fix_rela_dyn:
 	li	t3, RELOC_TYPE
 	bne	t5, t3, 10f		/* skip non-addned entries */
 
-	LREG	t3, -(REGBYTES*3)(t1)
+	LREG	t3, 0(t1)
 	li	t5, SYM_SIZE
 	mul	t0, t0, t5
 	add	s5, t4, t0
-	LREG	t0, -(REGBYTES)(t1)	/* t0 <-- addend */
+	LREG	t0, (REGBYTES * 2)(t1)	/* t0 <-- addend */
 	LREG	t5, REGBYTES(s5)
 	add	t5, t5, t0
 	add	t5, t5, t6		/* t5 <-- location to fix up in RAM */
 	add	t3, t3, t6		/* t3 <-- location to fix up in RAM */
 	SREG	t5, 0(t3)
 10:
-	addi	t1, t1, (REGBYTES*3)
-	ble	t1, t2, 6b
+	addi	t1, t1, (REGBYTES * 3)
+	blt	t1, t2, 6b
 
 /*
  * trap update