| Message ID | 20191025061027.20962-9-uboot@andestech.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | RISC-V AX25-AE350 support SPL | expand |
Hi Rick, On Fri, Oct 25, 2019 at 2:18 PM Andes <uboot@andestech.com> wrote: > > From: Rick Chen <rick@andestech.com> > > Add CPU2 and CPU3 informations in cpus node nits: information > to support four cores SMP booting. > > Signed-off-by: Rick Chen <rick@andestech.com> > Cc: KC Lin <kclin@andestech.com> > Cc: Alan Kao <alankao@andestech.com> > --- > arch/riscv/dts/ae350_32.dts | 51 ++++++++++++++++++++++++++++++++++++++++++--- > arch/riscv/dts/ae350_64.dts | 51 ++++++++++++++++++++++++++++++++++++++++++--- > 2 files changed, 96 insertions(+), 6 deletions(-) > > diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts > index 97b7cee..c794a7f 100644 > --- a/arch/riscv/dts/ae350_32.dts > +++ b/arch/riscv/dts/ae350_32.dts > @@ -62,6 +62,48 @@ > compatible = "riscv,cpu-intc"; > }; > }; > + CPU2: cpu@2 { > + device_type = "cpu"; > + reg = <2>; > + status = "okay"; > + compatible = "riscv"; > + riscv,isa = "rv32imafdc"; > + riscv,priv-major = <1>; > + riscv,priv-minor = <10>; > + mmu-type = "riscv,sv32"; > + clock-frequency = <60000000>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <32>; > + next-level-cache = <&L2>; > + CPU2_intc: interrupt-controller { > + #interrupt-cells = <1>; > + interrupt-controller; > + compatible = "riscv,cpu-intc"; > + }; > + }; > + CPU3: cpu@3 { > + device_type = "cpu"; > + reg = <3>; > + status = "okay"; > + compatible = "riscv"; > + riscv,isa = "rv32imafdc"; > + riscv,priv-major = <1>; > + riscv,priv-minor = <10>; > + mmu-type = "riscv,sv32"; > + clock-frequency = <60000000>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <32>; > + next-level-cache = <&L2>; > + CPU3_intc: interrupt-controller { > + #interrupt-cells = <1>; > + interrupt-controller; > + compatible = "riscv,cpu-intc"; > + }; > + }; > }; > > L2: l2-cache@e0500000 { > @@ -94,7 +136,8 @@ > interrupt-controller; > reg = <0xe4000000 0x2000000>; > riscv,ndev=<71>; > - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>; > + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9 > + &CPU2_intc 11 &CPU2_intc 9 &CPU3_intc 11 &CPU3_intc 9>; The indentation looks wrong. > }; > > plic1: interrupt-controller@e6400000 { > @@ -104,12 +147,14 @@ > interrupt-controller; > reg = <0xe6400000 0x400000>; > riscv,ndev=<2>; > - interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>; > + interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3 > + &CPU2_intc 3 &CPU3_intc 3>; > }; > > plmt0@e6000000 { > compatible = "riscv,plmt0"; > - interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>; > + interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7 > + &CPU2_intc 7 &CPU3_intc 7>; > reg = <0xe6000000 0x100000>; > }; > }; [snip] Regards, Bin
Hi Bin > > Hi Rick, > > On Fri, Oct 25, 2019 at 2:18 PM Andes <uboot@andestech.com> wrote: > > > > From: Rick Chen <rick@andestech.com> > > > > Add CPU2 and CPU3 informations in cpus node > > nits: information OK > > > to support four cores SMP booting. > > > > Signed-off-by: Rick Chen <rick@andestech.com> > > Cc: KC Lin <kclin@andestech.com> > > Cc: Alan Kao <alankao@andestech.com> > > --- > > arch/riscv/dts/ae350_32.dts | 51 ++++++++++++++++++++++++++++++++++++++++++--- > > arch/riscv/dts/ae350_64.dts | 51 ++++++++++++++++++++++++++++++++++++++++++--- > > 2 files changed, 96 insertions(+), 6 deletions(-) > > > > diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts > > index 97b7cee..c794a7f 100644 > > --- a/arch/riscv/dts/ae350_32.dts > > +++ b/arch/riscv/dts/ae350_32.dts > > @@ -62,6 +62,48 @@ > > compatible = "riscv,cpu-intc"; > > }; > > }; > > + CPU2: cpu@2 { > > + device_type = "cpu"; > > + reg = <2>; > > + status = "okay"; > > + compatible = "riscv"; > > + riscv,isa = "rv32imafdc"; > > + riscv,priv-major = <1>; > > + riscv,priv-minor = <10>; > > + mmu-type = "riscv,sv32"; > > + clock-frequency = <60000000>; > > + i-cache-size = <0x8000>; > > + i-cache-line-size = <32>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <32>; > > + next-level-cache = <&L2>; > > + CPU2_intc: interrupt-controller { > > + #interrupt-cells = <1>; > > + interrupt-controller; > > + compatible = "riscv,cpu-intc"; > > + }; > > + }; > > + CPU3: cpu@3 { > > + device_type = "cpu"; > > + reg = <3>; > > + status = "okay"; > > + compatible = "riscv"; > > + riscv,isa = "rv32imafdc"; > > + riscv,priv-major = <1>; > > + riscv,priv-minor = <10>; > > + mmu-type = "riscv,sv32"; > > + clock-frequency = <60000000>; > > + i-cache-size = <0x8000>; > > + i-cache-line-size = <32>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <32>; > > + next-level-cache = <&L2>; > > + CPU3_intc: interrupt-controller { > > + #interrupt-cells = <1>; > > + interrupt-controller; > > + compatible = "riscv,cpu-intc"; > > + }; > > + }; > > }; > > > > L2: l2-cache@e0500000 { > > @@ -94,7 +136,8 @@ > > interrupt-controller; > > reg = <0xe4000000 0x2000000>; > > riscv,ndev=<71>; > > - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>; > > + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9 > > + &CPU2_intc 11 &CPU2_intc 9 &CPU3_intc 11 &CPU3_intc 9>; > > The indentation looks wrong. OK. I will fix it. Thanks Rick > > > }; > > > > plic1: interrupt-controller@e6400000 { > > @@ -104,12 +147,14 @@ > > interrupt-controller; > > reg = <0xe6400000 0x400000>; > > riscv,ndev=<2>; > > - interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>; > > + interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3 > > + &CPU2_intc 3 &CPU3_intc 3>; > > }; > > > > plmt0@e6000000 { > > compatible = "riscv,plmt0"; > > - interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>; > > + interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7 > > + &CPU2_intc 7 &CPU3_intc 7>; > > reg = <0xe6000000 0x100000>; > > }; > > }; > > [snip] > > Regards, > Bin
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index 97b7cee..c794a7f 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -62,6 +62,48 @@ compatible = "riscv,cpu-intc"; }; }; + CPU2: cpu@2 { + device_type = "cpu"; + reg = <2>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv32imafdc"; + riscv,priv-major = <1>; + riscv,priv-minor = <10>; + mmu-type = "riscv,sv32"; + clock-frequency = <60000000>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; + CPU2_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + CPU3: cpu@3 { + device_type = "cpu"; + reg = <3>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv32imafdc"; + riscv,priv-major = <1>; + riscv,priv-minor = <10>; + mmu-type = "riscv,sv32"; + clock-frequency = <60000000>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; + CPU3_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; }; L2: l2-cache@e0500000 { @@ -94,7 +136,8 @@ interrupt-controller; reg = <0xe4000000 0x2000000>; riscv,ndev=<71>; - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9 + &CPU2_intc 11 &CPU2_intc 9 &CPU3_intc 11 &CPU3_intc 9>; }; plic1: interrupt-controller@e6400000 { @@ -104,12 +147,14 @@ interrupt-controller; reg = <0xe6400000 0x400000>; riscv,ndev=<2>; - interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>; + interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3 + &CPU2_intc 3 &CPU3_intc 3>; }; plmt0@e6000000 { compatible = "riscv,plmt0"; - interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>; + interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7 + &CPU2_intc 7 &CPU3_intc 7>; reg = <0xe6000000 0x100000>; }; }; diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index d8f00f8..b3d6d15 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -62,6 +62,48 @@ compatible = "riscv,cpu-intc"; }; }; + CPU2: cpu@2 { + device_type = "cpu"; + reg = <2>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <1>; + riscv,priv-minor = <10>; + mmu-type = "riscv,sv39"; + clock-frequency = <60000000>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; + CPU2_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + CPU3: cpu@3 { + device_type = "cpu"; + reg = <3>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <1>; + riscv,priv-minor = <10>; + mmu-type = "riscv,sv39"; + clock-frequency = <60000000>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; + CPU3_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; }; L2: l2-cache@e0500000 { @@ -94,7 +136,8 @@ interrupt-controller; reg = <0x0 0xe4000000 0x0 0x2000000>; riscv,ndev=<71>; - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9 + &CPU2_intc 11 &CPU2_intc 9 &CPU3_intc 11 &CPU3_intc 9>; }; plic1: interrupt-controller@e6400000 { @@ -104,12 +147,14 @@ interrupt-controller; reg = <0x0 0xe6400000 0x0 0x400000>; riscv,ndev=<2>; - interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>; + interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3 + &CPU2_intc 3 &CPU3_intc 3>; }; plmt0@e6000000 { compatible = "riscv,plmt0"; - interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>; + interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7 + &CPU2_intc 7 &CPU3_intc 7>; reg = <0x0 0xe6000000 0x0 0x100000>; }; };