| Message ID | 20191025061027.20962-2-uboot@andestech.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | RISC-V AX25-AE350 support SPL | expand |
Hi Rick, On Fri, Oct 25, 2019 at 2:17 PM Andes <uboot@andestech.com> wrote: > > From: Rick Chen <rick@andestech.com> > > The U-Boot SPL will boot in M mode and load the > FIT image which include OpenSbi and U-Boot proper nits: OpenSBI > images. After loading progress, it will jump to > OpenSbi first and then U-Boot proper which will ditto > run in S mode. > > Signed-off-by: Rick Chen <rick@andestech.com> > Cc: KC Lin <kclin@andestech.com> > Cc: Alan Kao <alankao@andestech.com> > --- > arch/riscv/cpu/ax25/Kconfig | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig > index d411a79..8d8d71d 100644 > --- a/arch/riscv/cpu/ax25/Kconfig > +++ b/arch/riscv/cpu/ax25/Kconfig > @@ -6,7 +6,9 @@ config RISCV_NDS > imply RISCV_TIMER > imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) > imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE) > - imply V5L2_CACHE Why this is removed? > + imply SPL_CPU_SUPPORT > + imply SPL_OPENSBI > + imply SPL_LOAD_FIT > help > Run U-Boot on AndeStar V5 platforms and use some specific features > which are provided by Andes Technology AndeStar V5 families. > -- Regards, Bin
Hi Bin > > Hi Rick, > > On Fri, Oct 25, 2019 at 2:17 PM Andes <uboot@andestech.com> wrote: > > > > From: Rick Chen <rick@andestech.com> > > > > The U-Boot SPL will boot in M mode and load the > > FIT image which include OpenSbi and U-Boot proper > > nits: OpenSBI OK > > > images. After loading progress, it will jump to > > OpenSbi first and then U-Boot proper which will > > ditto OK > > > run in S mode. > > > > Signed-off-by: Rick Chen <rick@andestech.com> > > Cc: KC Lin <kclin@andestech.com> > > Cc: Alan Kao <alankao@andestech.com> > > --- > > arch/riscv/cpu/ax25/Kconfig | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig > > index d411a79..8d8d71d 100644 > > --- a/arch/riscv/cpu/ax25/Kconfig > > +++ b/arch/riscv/cpu/ax25/Kconfig > > @@ -6,7 +6,9 @@ config RISCV_NDS > > imply RISCV_TIMER > > imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) > > imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE) > > - imply V5L2_CACHE > > Why this is removed? Without CACHE_SUPPORT, the compiling will fail while enable V5l2_CACHE. That is why I remove it. I hope it can be enable manually. Because it will enlarge U-Boot SPL size. Thanks Rick > > > + imply SPL_CPU_SUPPORT > > + imply SPL_OPENSBI > > + imply SPL_LOAD_FIT > > help > > Run U-Boot on AndeStar V5 platforms and use some specific features > > which are provided by Andes Technology AndeStar V5 families. > > -- > > Regards, > Bin
Hi Rick, On Wed, Oct 30, 2019 at 8:42 AM Rick Chen <rickchen36@gmail.com> wrote: > > Hi Bin > > > > > Hi Rick, > > > > On Fri, Oct 25, 2019 at 2:17 PM Andes <uboot@andestech.com> wrote: > > > > > > From: Rick Chen <rick@andestech.com> > > > > > > The U-Boot SPL will boot in M mode and load the > > > FIT image which include OpenSbi and U-Boot proper > > > > nits: OpenSBI > > OK > > > > > > images. After loading progress, it will jump to > > > OpenSbi first and then U-Boot proper which will > > > > ditto > > OK > > > > > > run in S mode. > > > > > > Signed-off-by: Rick Chen <rick@andestech.com> > > > Cc: KC Lin <kclin@andestech.com> > > > Cc: Alan Kao <alankao@andestech.com> > > > --- > > > arch/riscv/cpu/ax25/Kconfig | 4 +++- > > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > > > diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig > > > index d411a79..8d8d71d 100644 > > > --- a/arch/riscv/cpu/ax25/Kconfig > > > +++ b/arch/riscv/cpu/ax25/Kconfig > > > @@ -6,7 +6,9 @@ config RISCV_NDS > > > imply RISCV_TIMER > > > imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) > > > imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE) > > > - imply V5L2_CACHE > > > > Why this is removed? > > Without CACHE_SUPPORT, the compiling will fail while enable V5l2_CACHE. > That is why I remove it. I hope it can be enable manually. > Because it will enlarge U-Boot SPL size. > Could you please describe it in the commit message? Regards, Bin
Hi Bin > > Hi Rick, > > On Wed, Oct 30, 2019 at 8:42 AM Rick Chen <rickchen36@gmail.com> wrote: > > > > Hi Bin > > > > > > > > Hi Rick, > > > > > > On Fri, Oct 25, 2019 at 2:17 PM Andes <uboot@andestech.com> wrote: > > > > > > > > From: Rick Chen <rick@andestech.com> > > > > > > > > The U-Boot SPL will boot in M mode and load the > > > > FIT image which include OpenSbi and U-Boot proper > > > > > > nits: OpenSBI > > > > OK > > > > > > > > > images. After loading progress, it will jump to > > > > OpenSbi first and then U-Boot proper which will > > > > > > ditto > > > > OK > > > > > > > > > run in S mode. > > > > > > > > Signed-off-by: Rick Chen <rick@andestech.com> > > > > Cc: KC Lin <kclin@andestech.com> > > > > Cc: Alan Kao <alankao@andestech.com> > > > > --- > > > > arch/riscv/cpu/ax25/Kconfig | 4 +++- > > > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig > > > > index d411a79..8d8d71d 100644 > > > > --- a/arch/riscv/cpu/ax25/Kconfig > > > > +++ b/arch/riscv/cpu/ax25/Kconfig > > > > @@ -6,7 +6,9 @@ config RISCV_NDS > > > > imply RISCV_TIMER > > > > imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) > > > > imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE) > > > > - imply V5L2_CACHE > > > > > > Why this is removed? > > > > Without CACHE_SUPPORT, the compiling will fail while enable V5l2_CACHE. > > That is why I remove it. I hope it can be enable manually. > > Because it will enlarge U-Boot SPL size. > > > > Could you please describe it in the commit message? OK. I will add it. Thanks Rick > > Regards, > Bin
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index d411a79..8d8d71d 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -6,7 +6,9 @@ config RISCV_NDS imply RISCV_TIMER imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE) - imply V5L2_CACHE + imply SPL_CPU_SUPPORT + imply SPL_OPENSBI + imply SPL_LOAD_FIT help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families.