Message ID | 20191025061027.20962-8-uboot@andestech.com |
---|---|
State | Superseded |
Delegated to: | Andes |
Headers | show |
Series | RISC-V AX25-AE350 support SPL | expand |
Hi Rick, On Fri, Oct 25, 2019 at 2:18 PM Andes <uboot@andestech.com> wrote: > > From: Rick Chen <rick@andestech.com> > > For RV64, it will use sd instruction to clear t0 > register, and the increament will be 8 bytes. So > if the difference between__bss_strat and __bss_end > was not 8 bytes aligned, the clear bss loop will > overflow and acks like system hang. > > Signed-off-by: Rick Chen <rick@andestech.com> > Cc: KC Lin <kclin@andestech.com> > Cc: Alan Kao <alankao@andestech.com> > --- > arch/riscv/cpu/start.S | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > index 0a2ce6d..ee6d471 100644 > --- a/arch/riscv/cpu/start.S > +++ b/arch/riscv/cpu/start.S > @@ -174,7 +174,7 @@ spl_clear_bss: > spl_clear_bss_loop: > SREG zero, 0(t0) > addi t0, t0, REGBYTES > - bne t0, t1, spl_clear_bss_loop > + blt t0, t1, spl_clear_bss_loop This leaves bss section not completely zeroed. > > spl_stack_gd_setup: > jal spl_relocate_stack_gd > @@ -324,7 +324,7 @@ clear_bss: > clbss_l: > SREG zero, 0(t0) /* clear loop... */ > addi t0, t0, REGBYTES > - bne t0, t1, clbss_l > + blt t0, t1, clbss_l > > relocate_secondary_harts: > #ifdef CONFIG_SMP > -- Regards, Bin
Hi Bin > > Hi Rick, > > On Fri, Oct 25, 2019 at 2:18 PM Andes <uboot@andestech.com> wrote: > > > > From: Rick Chen <rick@andestech.com> > > > > For RV64, it will use sd instruction to clear t0 > > register, and the increament will be 8 bytes. So > > if the difference between__bss_strat and __bss_end > > was not 8 bytes aligned, the clear bss loop will > > overflow and acks like system hang. > > > > Signed-off-by: Rick Chen <rick@andestech.com> > > Cc: KC Lin <kclin@andestech.com> > > Cc: Alan Kao <alankao@andestech.com> > > --- > > arch/riscv/cpu/start.S | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > > index 0a2ce6d..ee6d471 100644 > > --- a/arch/riscv/cpu/start.S > > +++ b/arch/riscv/cpu/start.S > > @@ -174,7 +174,7 @@ spl_clear_bss: > > spl_clear_bss_loop: > > SREG zero, 0(t0) > > addi t0, t0, REGBYTES > > - bne t0, t1, spl_clear_bss_loop > > + blt t0, t1, spl_clear_bss_loop > > This leaves bss section not completely zeroed. I don't think this will clear bss section incompletely. Can you check it again ? Or explain more details why you think so ? Thanks Rick > > > > > spl_stack_gd_setup: > > jal spl_relocate_stack_gd > > @@ -324,7 +324,7 @@ clear_bss: > > clbss_l: > > SREG zero, 0(t0) /* clear loop... */ > > addi t0, t0, REGBYTES > > - bne t0, t1, clbss_l > > + blt t0, t1, clbss_l > > > > relocate_secondary_harts: > > #ifdef CONFIG_SMP > > -- > > Regards, > Bin
Hi Rick, On Thu, Oct 31, 2019 at 11:10 AM Rick Chen <rickchen36@gmail.com> wrote: > > Hi Bin > > > > > Hi Rick, > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes <uboot@andestech.com> wrote: > > > > > > From: Rick Chen <rick@andestech.com> > > > > > > For RV64, it will use sd instruction to clear t0 > > > register, and the increament will be 8 bytes. So > > > if the difference between__bss_strat and __bss_end > > > was not 8 bytes aligned, the clear bss loop will > > > overflow and acks like system hang. > > > > > > Signed-off-by: Rick Chen <rick@andestech.com> > > > Cc: KC Lin <kclin@andestech.com> > > > Cc: Alan Kao <alankao@andestech.com> > > > --- > > > arch/riscv/cpu/start.S | 4 ++-- > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > > > index 0a2ce6d..ee6d471 100644 > > > --- a/arch/riscv/cpu/start.S > > > +++ b/arch/riscv/cpu/start.S > > > @@ -174,7 +174,7 @@ spl_clear_bss: > > > spl_clear_bss_loop: > > > SREG zero, 0(t0) > > > addi t0, t0, REGBYTES > > > - bne t0, t1, spl_clear_bss_loop > > > + blt t0, t1, spl_clear_bss_loop > > > > This leaves bss section not completely zeroed. > > I don't think this will clear bss section incompletely. > Can you check it again ? > Or explain more details why you think so ? > Sorry I meant to say the other way around. This incorrectly clear the last a few bytes that are less than REGBYTES to zero. Regards, Bin
Hi Bin > > Hi Rick, > > On Thu, Oct 31, 2019 at 11:10 AM Rick Chen <rickchen36@gmail.com> wrote: > > > > Hi Bin > > > > > > > > Hi Rick, > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes <uboot@andestech.com> wrote: > > > > > > > > From: Rick Chen <rick@andestech.com> > > > > > > > > For RV64, it will use sd instruction to clear t0 > > > > register, and the increament will be 8 bytes. So > > > > if the difference between__bss_strat and __bss_end > > > > was not 8 bytes aligned, the clear bss loop will > > > > overflow and acks like system hang. > > > > > > > > Signed-off-by: Rick Chen <rick@andestech.com> > > > > Cc: KC Lin <kclin@andestech.com> > > > > Cc: Alan Kao <alankao@andestech.com> > > > > --- > > > > arch/riscv/cpu/start.S | 4 ++-- > > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > > > > index 0a2ce6d..ee6d471 100644 > > > > --- a/arch/riscv/cpu/start.S > > > > +++ b/arch/riscv/cpu/start.S > > > > @@ -174,7 +174,7 @@ spl_clear_bss: > > > > spl_clear_bss_loop: > > > > SREG zero, 0(t0) > > > > addi t0, t0, REGBYTES > > > > - bne t0, t1, spl_clear_bss_loop > > > > + blt t0, t1, spl_clear_bss_loop > > > > > > This leaves bss section not completely zeroed. > > > > I don't think this will clear bss section incompletely. > > Can you check it again ? > > Or explain more details why you think so ? > > > > Sorry I meant to say the other way around. This incorrectly clear the > last a few bytes that are less than REGBYTES to zero. > OK . I will also modify as ALIGN(8) in ld to avoid this boundary exceeding. Thanks Rick > Regards, > Bin
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 0a2ce6d..ee6d471 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -174,7 +174,7 @@ spl_clear_bss: spl_clear_bss_loop: SREG zero, 0(t0) addi t0, t0, REGBYTES - bne t0, t1, spl_clear_bss_loop + blt t0, t1, spl_clear_bss_loop spl_stack_gd_setup: jal spl_relocate_stack_gd @@ -324,7 +324,7 @@ clear_bss: clbss_l: SREG zero, 0(t0) /* clear loop... */ addi t0, t0, REGBYTES - bne t0, t1, clbss_l + blt t0, t1, clbss_l relocate_secondary_harts: #ifdef CONFIG_SMP