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riscv: Adding RISC-V CPU and timer driver
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| 20 patches
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Apply
Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[U-Boot,v2,01/20] riscv: add Kconfig entries for the code model
riscv: Adding RISC-V CPU and timer driver
- - - -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,02/20] dm: cpu: Add timebase frequency to the platdata
riscv: Adding RISC-V CPU and timer driver
- - 2 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,03/20] riscv: qemu: Create a simple-bus driver for the soc node
riscv: Adding RISC-V CPU and timer driver
- - 1 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,04/20] cpu: Add a RISC-V CPU driver
riscv: Adding RISC-V CPU and timer driver
- - 1 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,05/20] timer: Add generic driver for RISC-V privileged architecture defined timer
riscv: Adding RISC-V CPU and timer driver
- - 1 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,06/20] riscv: ax25: Hide the ax25-specific Kconfig option
riscv: Adding RISC-V CPU and timer driver
- - 1 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,07/20] riscv: Introduce a Kconfig option for machine mode
riscv: Adding RISC-V CPU and timer driver
- - 1 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,08/20] riscv: Add a SYSCON driver for SiFive's Core Local Interruptor
riscv: Adding RISC-V CPU and timer driver
- - - -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,09/20] riscv: Implement riscv_get_time() API using rdtime instruction
riscv: Adding RISC-V CPU and timer driver
- - 1 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,10/20] riscv: qemu: Add platform-specific Kconfig options
riscv: Adding RISC-V CPU and timer driver
- - 1 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,11/20] riscv: Enlarge the default SYS_MALLOC_F_LEN
riscv: Adding RISC-V CPU and timer driver
- - 1 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,12/20] riscv: Probe cpus during boot
riscv: Adding RISC-V CPU and timer driver
- - 1 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,13/20] riscv: Add CSR numbers
riscv: Adding RISC-V CPU and timer driver
- - 1 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,14/20] riscv: Add exception codes for xcause register
riscv: Adding RISC-V CPU and timer driver
- - 1 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,15/20] riscv: Add indirect stringification to csr_xxx ops
riscv: Adding RISC-V CPU and timer driver
- - 1 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,16/20] riscv: Do some basic architecture level cpu initialization
riscv: Adding RISC-V CPU and timer driver
- - - -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,17/20] riscv: Move trap handler codes to mtrap.S
riscv: Adding RISC-V CPU and timer driver
- - 1 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,18/20] riscv: Fix context restore before returning from trap handler
riscv: Adding RISC-V CPU and timer driver
- - 1 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,19/20] riscv: Return to previous privilege level after trap handling
riscv: Adding RISC-V CPU and timer driver
- - 1 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded
[U-Boot,v2,20/20] riscv: Adjust the _exit_trap() position to come before handle_trap()
riscv: Adding RISC-V CPU and timer driver
- - 1 -
-
-
-
2018-12-07
Bin Meng
Andes
Superseded