| Message ID | 1544192072-28764-8-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | riscv: Adding RISC-V CPU and timer driver | expand |
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote: > From: Anup Patel <anup@brainfault.org> > > So far we have a Kconfig option for supervisor mode. This adds an > option for the machine mode. > > Signed-off-by: Anup Patel <anup@brainfault.org> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > > --- > > Changes in v2: > - incorporated and reworked Anup's S-mode timer patch > @ http://patchwork.ozlabs.org/patch/1006663/ > > arch/riscv/Kconfig | 21 ++++++++++++++++----- > 1 file changed, 16 insertions(+), 5 deletions(-) > Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6d85ac9..55c60e4 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -62,6 +62,22 @@ config CMODEL_MEDANY endchoice +choice + prompt "Run Mode" + default RISCV_MMODE + +config RISCV_MMODE + bool "Machine" + help + Choose this option to build U-Boot for RISC-V M-Mode. + +config RISCV_SMODE + bool "Supervisor" + help + Choose this option to build U-Boot for RISC-V S-Mode. + +endchoice + config RISCV_ISA_C bool "Emit compressed instructions" default y @@ -73,11 +89,6 @@ config RISCV_ISA_C config RISCV_ISA_A def_bool y -config RISCV_SMODE - bool "Run in S-Mode" - help - Enable this option to build U-Boot for RISC-V S-Mode - config 32BIT bool