Show patches with: Submitter = Alistair Francis       |    State = Action Required       |    Archived = No       |   1748 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,09/18] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,08/18] target/riscv: Add sifive_plic vmstate [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,07/18] target/riscv: Add V extension state description [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 2 - --- 2020-10-29 Alistair Francis New
[PULL,06/18] target/riscv: Add H extension state description [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,05/18] target/riscv: Add PMP state description [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,04/18] target/riscv: Add basic vmstate description of CPU [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,03/18] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,02/18] hw/riscv: virt: Allow passing custom DTB [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,00/18] riscv-to-apply queue - - - - --- 2020-10-29 Alistair Francis New
[v2,5/5] target/riscv: Split the Hypervisor execute load helpers Fix the Hypervisor access functions - - - - --- 2020-10-28 Alistair Francis New
[v2,4/5] target/riscv: Remove the hyp load and store functions Fix the Hypervisor access functions - - - - --- 2020-10-28 Alistair Francis New
[v2,3/5] target/riscv: Remove the HS_TWO_STAGE flag Fix the Hypervisor access functions - - 1 - --- 2020-10-28 Alistair Francis New
[v2,2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses Fix the Hypervisor access functions - - 1 - --- 2020-10-28 Alistair Francis New
[v2,1/5] target/riscv: Add a virtualised MMU Mode Fix the Hypervisor access functions - - - - --- 2020-10-28 Alistair Francis New
[v1,16/16] target/riscv: Consolidate *statush registers RISC-V: Start to remove xlen preprocess - - - - --- 2020-10-23 Alistair Francis New
[v1,15/16] target/riscv: Convert the get/set_field() to support 64-bit values RISC-V: Start to remove xlen preprocess - - - - --- 2020-10-23 Alistair Francis New
[v1,14/16] target/riscv: cpu: Set XLEN independently from target RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-10-23 Alistair Francis New
[v1,13/16] target/riscv: csr: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - - - --- 2020-10-23 Alistair Francis New
[v1,12/16] target/riscv: cpu_helper: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - - - --- 2020-10-23 Alistair Francis New
[v1,11/16] target/riscv: cpu: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - 1 - --- 2020-10-23 Alistair Francis New
[v1,10/16] target/riscv: Specify the XLEN for CPUs RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-10-23 Alistair Francis New
[v1,09/16] target/riscv: Add a riscv_cpu_is_32bit() helper function RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-10-23 Alistair Francis New
[v1,08/16] target/riscv: fpu_helper: Match function defs in HELPER macros RISC-V: Start to remove xlen preprocess - - - - --- 2020-10-23 Alistair Francis New
[v1,07/16] hw/riscv: sifive_u: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - - - --- 2020-10-23 Alistair Francis New
[v1,06/16] hw/riscv: spike: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - 1 - --- 2020-10-23 Alistair Francis New
[v1,05/16] hw/riscv: virt: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-10-23 Alistair Francis New
[v1,04/16] hw/riscv: boot: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-10-23 Alistair Francis New
[v1,03/16] riscv: virt: Remove target macro conditionals RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-10-23 Alistair Francis New
[v1,02/16] riscv: spike: Remove target macro conditionals RISC-V: Start to remove xlen preprocess - - 1 - --- 2020-10-23 Alistair Francis New
[v1,01/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-10-23 Alistair Francis New
[v1,5/5] target/riscv: Split the Hypervisor execute load helpers Fix the Hypervisor access functions - - - - --- 2020-10-23 Alistair Francis New
[v1,4/5] target/riscv: Remove the hyp load and store functions Fix the Hypervisor access functions - - - - --- 2020-10-23 Alistair Francis New
[v1,3/5] target/riscv: Remove the HS_TWO_STAGE flag Fix the Hypervisor access functions - - - - --- 2020-10-23 Alistair Francis New
[v1,2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses Fix the Hypervisor access functions - - - - --- 2020-10-23 Alistair Francis New
[v1,1/5] target/riscv: Add a virtualised MMU Mode Fix the Hypervisor access functions - - - - --- 2020-10-23 Alistair Francis New
[PULL,12/12] hw/misc/sifive_u_otp: Add backend drive support [PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() 1 - 1 1 --- 2020-10-23 Alistair Francis New
[PULL,11/12] hw/misc/sifive_u_otp: Add write function and write-once protection [PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() - - 2 1 --- 2020-10-23 Alistair Francis New
[PULL,10/12] target/riscv: raise exception to HS-mode at get_physical_address [PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() - - 1 - --- 2020-10-23 Alistair Francis New
[PULL,09/12] hw/riscv: Load the kernel after the firmware [PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() - - 2 1 --- 2020-10-23 Alistair Francis New
[PULL,08/12] hw/riscv: Add a riscv_is_32_bit() function [PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() - - 2 1 --- 2020-10-23 Alistair Francis New
[PULL,07/12] hw/riscv: Return the end address of the loaded firmware [PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() - - 2 1 --- 2020-10-23 Alistair Francis New
[PULL,06/12] hw/riscv: sifive_u: Allow specifying the CPU [PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() - - 2 1 --- 2020-10-23 Alistair Francis New
[PULL,05/12] target/riscv: Fix implementation of HLVX.WU instruction [PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() - 1 2 - --- 2020-10-23 Alistair Francis New
[PULL,04/12] target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt [PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() - - 1 - --- 2020-10-23 Alistair Francis New
[PULL,03/12] target/riscv: Fix update of hstatus.SPVP [PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() - - 1 - --- 2020-10-23 Alistair Francis New
[PULL,02/12] hw/intc: Move sifive_plic.h to the include directory [PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() - 1 2 - --- 2020-10-23 Alistair Francis New
[PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() [PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() - - 1 - --- 2020-10-23 Alistair Francis New
[PULL,00/12] riscv-to-apply queue - - - - --- 2020-10-23 Alistair Francis New
[v2,4/4] hw/riscv: Load the kernel after the firmware Allow loading a no MMU kernel - - 2 1 --- 2020-10-14 Alistair Francis New
[v2,3/4] hw/riscv: Add a riscv_is_32_bit() function Allow loading a no MMU kernel - - 2 1 --- 2020-10-14 Alistair Francis New
[v2,2/4] hw/riscv: Return the end address of the loaded firmware Allow loading a no MMU kernel - - 2 1 --- 2020-10-14 Alistair Francis New
[v2,1/4] hw/riscv: sifive_u: Allow specifying the CPU Allow loading a no MMU kernel - - 2 1 --- 2020-10-14 Alistair Francis New
[v2,1/1] register: Remove unnecessary NULL check [v2,1/1] register: Remove unnecessary NULL check - - - - --- 2020-10-02 Alistair Francis New
[v1,1/1] register: Remove unnecessary NULL check [v1,1/1] register: Remove unnecessary NULL check - - - - --- 2020-10-02 Alistair Francis New
[v1,4/4] hw/riscv: Load the kernel after the firmware Allow loading a no MMU kernel - - - - --- 2020-10-02 Alistair Francis New
[v1,3/4] hw/riscv: Add a riscv_is_32_bit() function Allow loading a no MMU kernel - - - - --- 2020-10-02 Alistair Francis New
[v1,2/4] hw/riscv: Return the end address of the loaded firmware Allow loading a no MMU kernel - - - - --- 2020-10-02 Alistair Francis New
[v1,1/4] hw/riscv: sifive_u: Allow specifying the CPU Allow loading a no MMU kernel - - 1 - --- 2020-10-02 Alistair Francis New
[v2,1/1] riscv: Convert interrupt logs to use qemu_log_mask() [v2,1/1] riscv: Convert interrupt logs to use qemu_log_mask() - - 1 - --- 2020-10-02 Alistair Francis New
[v1,1/1] riscv: Convert interrupt logs to use qemu_log_mask() [v1,1/1] riscv: Convert interrupt logs to use qemu_log_mask() - - 1 - --- 2020-09-27 Alistair Francis New
[PULL,2/2] core/register: Specify instance_size in the TypeInfo [PULL,1/2] load_elf: Remove unused address variables from callers - - 1 - --- 2020-09-27 Alistair Francis New
[PULL,1/2] load_elf: Remove unused address variables from callers [PULL,1/2] load_elf: Remove unused address variables from callers 2 - 2 - --- 2020-09-27 Alistair Francis New
[PULL,0/2] register queue - - - - --- 2020-09-27 Alistair Francis New
[PULL,30/30] hw/riscv: Sort the Kconfig options in alphabetical order [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,29/30] hw/riscv: Drop CONFIG_SIFIVE [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,28/30] hw/riscv: Always build riscv_hart.c [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,27/30] hw/riscv: Move sifive_test model to hw/misc [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,26/30] hw/riscv: Move sifive_uart model to hw/char [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,25/30] hw/riscv: Move riscv_htif model to hw/char [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,24/30] hw/riscv: Move sifive_plic model to hw/intc [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,23/30] hw/riscv: Move sifive_clint model to hw/intc [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,22/30] hw/riscv: Move sifive_gpio model to hw/gpio [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,21/30] hw/riscv: Move sifive_u_otp model to hw/misc [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,20/30] hw/riscv: Move sifive_u_prci model to hw/misc [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,19/30] hw/riscv: Move sifive_e_prci model to hw/misc [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,18/30] hw/riscv: sifive_u: Connect a DMA controller [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,17/30] hw/riscv: clint: Avoid using hard-coded timebase frequency [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,16/30] hw/riscv: microchip_pfsoc: Hook GPIO controllers [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 2 - --- 2020-09-10 Alistair Francis New
[PULL,15/30] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 2 - --- 2020-09-10 Alistair Francis New
[PULL,14/30] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 2 - --- 2020-09-10 Alistair Francis New
[PULL,13/30] hw/net: cadence_gem: Add a new 'phy-addr' property [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 3 - --- 2020-09-10 Alistair Francis New
[PULL,12/30] hw/riscv: microchip_pfsoc: Connect a DMA controller [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,11/30] hw/dma: Add SiFive platform DMA controller emulation [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap 1 - - - --- 2020-09-10 Alistair Francis New
[PULL,10/30] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 2 - --- 2020-09-10 Alistair Francis New
[PULL,09/30] hw/sd: Add Cadence SDHCI emulation [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap 2 - - - --- 2020-09-10 Alistair Francis New
[PULL,08/30] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,06/30] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,05/30] target/riscv: cpu: Set reset vector based on the configured property value [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 2 - --- 2020-09-10 Alistair Francis New
[PULL,04/30] hw/riscv: hart: Add a new 'resetvec' property [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 2 - --- 2020-09-10 Alistair Francis New
[PULL,03/30] target/riscv: cpu: Add a new 'resetvec' property [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 2 - --- 2020-09-10 Alistair Francis New
[PULL,02/30] riscv: sifive_test: Allow 16-bit writes to memory region [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap 1 2 1 - --- 2020-09-10 Alistair Francis New
[PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,00/30] riscv-to-apply queue - - - - --- 2020-09-10 Alistair Francis New
[PULL,00/30] riscv-to-apply queue - - - - --- 2020-09-10 Alistair Francis New
[PULL,18/18] target/riscv: Support the Virtual Instruction fault [PULL,01/18] hw/riscv: Allow creating multiple instances of CLINT - - - - --- 2020-08-25 Alistair Francis New
[PULL,17/18] target/riscv: Return the exception from invalid CSR accesses [PULL,01/18] hw/riscv: Allow creating multiple instances of CLINT - - - - --- 2020-08-25 Alistair Francis New
[PULL,16/18] target/riscv: Support the v0.6 Hypervisor extension CRSs [PULL,01/18] hw/riscv: Allow creating multiple instances of CLINT - - - - --- 2020-08-25 Alistair Francis New
[PULL,15/18] target/riscv: Only support little endian guests [PULL,01/18] hw/riscv: Allow creating multiple instances of CLINT - - - - --- 2020-08-25 Alistair Francis New
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