Show patches with: Submitter = Alistair Francis       |    State = Action Required       |    Archived = No       |   1748 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v4,13/16] target/riscv: cpu_helper: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess 1 - 3 1 --- 2020-12-16 Alistair Francis New
[v4,12/16] target/riscv: cpu: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess 1 - 3 1 --- 2020-12-16 Alistair Francis New
[v4,11/16] target/riscv: Specify the XLEN for CPUs RISC-V: Start to remove xlen preprocess 1 - 3 1 --- 2020-12-16 Alistair Francis New
[v4,10/16] target/riscv: Add a riscv_cpu_is_32bit() helper function RISC-V: Start to remove xlen preprocess 1 - 2 1 --- 2020-12-16 Alistair Francis New
[v4,09/16] target/riscv: fpu_helper: Match function defs in HELPER macros RISC-V: Start to remove xlen preprocess - - - - --- 2020-12-16 Alistair Francis New
[v4,08/16] hw/riscv: sifive_u: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess 1 - 2 1 --- 2020-12-16 Alistair Francis New
[v4,07/16] hw/riscv: spike: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess 1 - 2 - --- 2020-12-16 Alistair Francis New
[v4,06/16] hw/riscv: virt: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess 1 - 2 1 --- 2020-12-16 Alistair Francis New
[v4,05/16] hw/riscv: boot: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess 1 - 2 1 --- 2020-12-16 Alistair Francis New
[v4,04/16] riscv: virt: Remove target macro conditionals RISC-V: Start to remove xlen preprocess 1 - 2 1 --- 2020-12-16 Alistair Francis New
[v4,03/16] riscv: spike: Remove target macro conditionals RISC-V: Start to remove xlen preprocess 1 - 2 - --- 2020-12-16 Alistair Francis New
[v4,02/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU RISC-V: Start to remove xlen preprocess 1 - 2 1 --- 2020-12-16 Alistair Francis New
[v4,01/16] hw/riscv: Expand the is 32-bit check to support more CPUs RISC-V: Start to remove xlen preprocess 1 - 1 - --- 2020-12-16 Alistair Francis New
[v1,1/1] riscv/opentitan: Update the OpenTitan memory layout [v1,1/1] riscv/opentitan: Update the OpenTitan memory layout - - - - --- 2020-12-15 Alistair Francis New
[v3,15/15] target/riscv: cpu: Set XLEN independently from target RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-12-14 Alistair Francis New
[v3,14/15] target/riscv: csr: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - 1 - --- 2020-12-14 Alistair Francis New
[v3,13/15] target/riscv: cpu_helper: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - 1 - --- 2020-12-14 Alistair Francis New
[v3,12/15] target/riscv: cpu: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - 2 - --- 2020-12-14 Alistair Francis New
[v3,11/15] target/riscv: Specify the XLEN for CPUs RISC-V: Start to remove xlen preprocess - - 2 1 --- 2020-12-14 Alistair Francis New
[v3,10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-12-14 Alistair Francis New
[v3,09/15] target/riscv: fpu_helper: Match function defs in HELPER macros RISC-V: Start to remove xlen preprocess - - - - --- 2020-12-14 Alistair Francis New
[v3,08/15] hw/riscv: sifive_u: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - - - --- 2020-12-14 Alistair Francis New
[v3,07/15] hw/riscv: spike: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - 1 - --- 2020-12-14 Alistair Francis New
[v3,06/15] hw/riscv: virt: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-12-14 Alistair Francis New
[v3,05/15] hw/riscv: boot: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-12-14 Alistair Francis New
[v3,04/15] riscv: virt: Remove target macro conditionals RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-12-14 Alistair Francis New
[v3,03/15] riscv: spike: Remove target macro conditionals RISC-V: Start to remove xlen preprocess - - 1 - --- 2020-12-14 Alistair Francis New
[v3,02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-12-14 Alistair Francis New
[v3,01/15] hw/riscv: Expand the is 32-bit check to support more CPUs RISC-V: Start to remove xlen preprocess - - - - --- 2020-12-14 Alistair Francis New
[v2,15/15] target/riscv: cpu: Set XLEN independently from target RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-12-08 Alistair Francis New
[v2,14/15] target/riscv: csr: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - - - --- 2020-12-08 Alistair Francis New
[v2,13/15] target/riscv: cpu_helper: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - 1 - --- 2020-12-08 Alistair Francis New
[v2,12/15] target/riscv: cpu: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - 2 - --- 2020-12-08 Alistair Francis New
[v2,11/15] target/riscv: Specify the XLEN for CPUs RISC-V: Start to remove xlen preprocess - - 2 1 --- 2020-12-08 Alistair Francis New
[v2,10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-12-08 Alistair Francis New
[v2,09/15] target/riscv: fpu_helper: Match function defs in HELPER macros RISC-V: Start to remove xlen preprocess - - - - --- 2020-12-08 Alistair Francis New
[v2,08/15] hw/riscv: sifive_u: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - - - --- 2020-12-08 Alistair Francis New
[v2,07/15] hw/riscv: spike: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - 1 - --- 2020-12-08 Alistair Francis New
[v2,06/15] hw/riscv: virt: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-12-08 Alistair Francis New
[v2,05/15] hw/riscv: boot: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-12-08 Alistair Francis New
[v2,04/15] riscv: virt: Remove target macro conditionals RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-12-08 Alistair Francis New
[v2,03/15] riscv: spike: Remove target macro conditionals RISC-V: Start to remove xlen preprocess - - 1 - --- 2020-12-08 Alistair Francis New
[v2,02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU RISC-V: Start to remove xlen preprocess - - 1 1 --- 2020-12-08 Alistair Francis New
[v2,01/15] hw/riscv: Expand the is 32-bit check to support more CPUs RISC-V: Start to remove xlen preprocess - - - - --- 2020-12-08 Alistair Francis New
[v1,1/1] intc/ibex_plic: Clear interrupts that occur during claim process [v1,1/1] intc/ibex_plic: Clear interrupts that occur during claim process - - - 1 --- 2020-12-04 Alistair Francis New
[PULL,2/2] intc/ibex_plic: Ensure we don't loose interrupts [PULL,1/2] intc/ibex_plic: Fix some typos in the comments - - - - --- 2020-11-14 Alistair Francis New
[PULL,1/2] intc/ibex_plic: Fix some typos in the comments [PULL,1/2] intc/ibex_plic: Fix some typos in the comments - - - - --- 2020-11-14 Alistair Francis New
[PULL,0/2] riscv-to-apply queue - - - - --- 2020-11-14 Alistair Francis New
[v1,2/2] intc/ibex_plic: Ensure we don't loose interrupts [v1,1/2] intc/ibex_plic: Fix some typos in the comments - - - - --- 2020-11-11 Alistair Francis New
[v1,1/2] intc/ibex_plic: Fix some typos in the comments [v1,1/2] intc/ibex_plic: Fix some typos in the comments - - - - --- 2020-11-11 Alistair Francis New
[PULL,6/6] hw/intc/ibex_plic: Clear the claim register when read [PULL,1/6] target/riscv: Add a virtualised MMU Mode - - 1 - --- 2020-11-10 Alistair Francis New
[PULL,5/6] target/riscv: Split the Hypervisor execute load helpers [PULL,1/6] target/riscv: Add a virtualised MMU Mode - - 1 - --- 2020-11-10 Alistair Francis New
[PULL,4/6] target/riscv: Remove the hyp load and store functions [PULL,1/6] target/riscv: Add a virtualised MMU Mode - - 1 - --- 2020-11-10 Alistair Francis New
[PULL,3/6] target/riscv: Remove the HS_TWO_STAGE flag [PULL,1/6] target/riscv: Add a virtualised MMU Mode - - 1 - --- 2020-11-10 Alistair Francis New
[PULL,2/6] target/riscv: Set the virtualised MMU mode when doing hyp accesses [PULL,1/6] target/riscv: Add a virtualised MMU Mode - - 1 - --- 2020-11-10 Alistair Francis New
[PULL,1/6] target/riscv: Add a virtualised MMU Mode [PULL,1/6] target/riscv: Add a virtualised MMU Mode - - 1 - --- 2020-11-10 Alistair Francis New
[PULL,0/6] riscv-to-apply queue - - - - --- 2020-11-10 Alistair Francis New
[v1,1/1] hw/intc/ibex_plic: Clear the claim register when read [v1,1/1] hw/intc/ibex_plic: Clear the claim register when read - - 1 - --- 2020-11-06 Alistair Francis New
[v4,5/5] target/riscv: Split the Hypervisor execute load helpers Fix the Hypervisor access functions - - 1 - --- 2020-11-04 Alistair Francis New
[v4,4/5] target/riscv: Remove the hyp load and store functions Fix the Hypervisor access functions - - 1 - --- 2020-11-04 Alistair Francis New
[v4,3/5] target/riscv: Remove the HS_TWO_STAGE flag Fix the Hypervisor access functions - - 1 - --- 2020-11-04 Alistair Francis New
[v4,2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses Fix the Hypervisor access functions - - 1 - --- 2020-11-04 Alistair Francis New
[v4,1/5] target/riscv: Add a virtualised MMU Mode Fix the Hypervisor access functions - - 1 - --- 2020-11-04 Alistair Francis New
[v3,7/7] target/riscv: Split the Hypervisor execute load helpers Fix the Hypervisor access functions - - 1 - --- 2020-11-03 Alistair Francis New
[v3,6/7] target/riscv: Remove the Hypervisor access check function Fix the Hypervisor access functions - - - - --- 2020-11-03 Alistair Francis New
[v3,5/7] target/riscv: Remove the hyp load and store functions Fix the Hypervisor access functions - - - - --- 2020-11-03 Alistair Francis New
[v3,4/7] target/riscv: Remove the HS_TWO_STAGE flag Fix the Hypervisor access functions - - 1 - --- 2020-11-03 Alistair Francis New
[v3,3/7] target/riscv: Set the virtualised MMU mode when doing hyp accesses Fix the Hypervisor access functions - - 1 - --- 2020-11-03 Alistair Francis New
[v3,2/7] target/riscv: Add a virtualised MMU Mode Fix the Hypervisor access functions - - - - --- 2020-11-03 Alistair Francis New
[v3,1/7] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Fix the Hypervisor access functions - - 2 - --- 2020-11-03 Alistair Francis New
[v1,1/1] linux-user/syscall: Fix missing target_to_host_timespec64() check [v1,1/1] linux-user/syscall: Fix missing target_to_host_timespec64() check - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,19/19] target/riscv/csr.c : add space before the open parenthesis '(' [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 2 - --- 2020-11-03 Alistair Francis New
[PULL,v2,18/19] hw/riscv: microchip_pfsoc: Hook the I2C1 controller [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,17/19] hw/riscv: microchip_pfsoc: Correct DDR memory map [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,16/19] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,15/19] hw/riscv: microchip_pfsoc: Connect the SYSREG module [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,14/19] hw/misc: Add Microchip PolarFire SoC SYSREG module support [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,13/19] hw/riscv: microchip_pfsoc: Connect the IOSCB module [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,12/19] hw/misc: Add Microchip PolarFire SoC IOSCB module support [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,11/19] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,10/19] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,09/19] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,08/19] target/riscv: Add sifive_plic vmstate [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,07/19] target/riscv: Add V extension state description [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 2 - --- 2020-11-03 Alistair Francis New
[PULL,v2,06/19] target/riscv: Add H extension state description [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,05/19] target/riscv: Add PMP state description [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,04/19] target/riscv: Add basic vmstate description of CPU [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,03/19] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,02/19] hw/riscv: virt: Allow passing custom DTB [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,00/19] riscv-to-apply queue - - - - --- 2020-11-03 Alistair Francis New
[PULL,18/18] hw/riscv: microchip_pfsoc: Hook the I2C1 controller [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,17/18] hw/riscv: microchip_pfsoc: Correct DDR memory map [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,16/18] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,15/18] hw/riscv: microchip_pfsoc: Connect the SYSREG module [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,14/18] hw/misc: Add Microchip PolarFire SoC SYSREG module support [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,13/18] hw/riscv: microchip_pfsoc: Connect the IOSCB module [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,12/18] hw/misc: Add Microchip PolarFire SoC IOSCB module support [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,11/18] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,10/18] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
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