| Message ID | 16213739a6232aa4824c5a008e2f669e6e58fbcf.1603466725.git.alistair.francis@wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Fix the Hypervisor access functions | expand |
On 10/23/20 8:26 AM, Alistair Francis wrote: > +++ b/target/riscv/cpu-param.h > @@ -18,6 +18,6 @@ > # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ > #endif > #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ > -#define NB_MMU_MODES 4 > +#define NB_MMU_MODES 8 Is there really a PRV_M + virt enabled state? > +#define TB_FLAGS_PRIV_MMU_MASK 3 ... > - int mode = mmu_idx; > + int mode = mmu_idx & 0x3; Use that MASK here? r~
On Fri, Oct 23, 2020 at 12:13 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > On 10/23/20 8:26 AM, Alistair Francis wrote: > > +++ b/target/riscv/cpu-param.h > > @@ -18,6 +18,6 @@ > > # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ > > #endif > > #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ > > -#define NB_MMU_MODES 4 > > +#define NB_MMU_MODES 8 > > Is there really a PRV_M + virt enabled state? No, there isn't. > > > +#define TB_FLAGS_PRIV_MMU_MASK 3 > ... > > - int mode = mmu_idx; > > + int mode = mmu_idx & 0x3; > > Use that MASK here? Good idea. Alistair > > > r~
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index 664fc1d371..502ed6489e 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -18,6 +18,6 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ #endif #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ -#define NB_MMU_MODES 4 +#define NB_MMU_MODES 8 #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de4705bb57..8ac01f3a64 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -365,7 +365,9 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); -#define TB_FLAGS_MMU_MASK 3 +#define TB_FLAGS_MMU_MASK 7 +#define TB_FLAGS_PRIV_MMU_MASK 3 +#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) #define TB_FLAGS_MSTATUS_FS MSTATUS_FS typedef CPURISCVState CPUArchState; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4652082df1..46b62a0f37 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -30,6 +30,10 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #ifdef CONFIG_USER_ONLY return 0; #else + if (riscv_cpu_virt_enabled(env)) { + return env->priv | TB_FLAGS_PRIV_HYP_ACCESS_MASK; + } + return env->priv; #endif } @@ -336,7 +340,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, * (riscv_cpu_do_interrupt) is correct */ MemTxResult res; MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; - int mode = mmu_idx; + int mode = mmu_idx & 0x3; bool use_background = false; /*
Add a new MMU mode that includes the current virt mode. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu-param.h | 2 +- target/riscv/cpu.h | 4 +++- target/riscv/cpu_helper.c | 6 +++++- 3 files changed, 9 insertions(+), 3 deletions(-)