Show patches with: Series = [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap       |    State = Action Required       |    Archived = No       |   30 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,30/30] hw/riscv: Sort the Kconfig options in alphabetical order [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,29/30] hw/riscv: Drop CONFIG_SIFIVE [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,28/30] hw/riscv: Always build riscv_hart.c [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,27/30] hw/riscv: Move sifive_test model to hw/misc [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,26/30] hw/riscv: Move sifive_uart model to hw/char [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,25/30] hw/riscv: Move riscv_htif model to hw/char [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,24/30] hw/riscv: Move sifive_plic model to hw/intc [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,23/30] hw/riscv: Move sifive_clint model to hw/intc [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,22/30] hw/riscv: Move sifive_gpio model to hw/gpio [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,21/30] hw/riscv: Move sifive_u_otp model to hw/misc [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,20/30] hw/riscv: Move sifive_u_prci model to hw/misc [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,19/30] hw/riscv: Move sifive_e_prci model to hw/misc [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,18/30] hw/riscv: sifive_u: Connect a DMA controller [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,17/30] hw/riscv: clint: Avoid using hard-coded timebase frequency [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,16/30] hw/riscv: microchip_pfsoc: Hook GPIO controllers [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 2 - --- 2020-09-10 Alistair Francis New
[PULL,15/30] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 2 - --- 2020-09-10 Alistair Francis New
[PULL,14/30] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 2 - --- 2020-09-10 Alistair Francis New
[PULL,13/30] hw/net: cadence_gem: Add a new 'phy-addr' property [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 3 - --- 2020-09-10 Alistair Francis New
[PULL,12/30] hw/riscv: microchip_pfsoc: Connect a DMA controller [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,11/30] hw/dma: Add SiFive platform DMA controller emulation [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap 1 - - - --- 2020-09-10 Alistair Francis New
[PULL,10/30] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 2 - --- 2020-09-10 Alistair Francis New
[PULL,09/30] hw/sd: Add Cadence SDHCI emulation [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap 2 - - - --- 2020-09-10 Alistair Francis New
[PULL,08/30] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,06/30] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,05/30] target/riscv: cpu: Set reset vector based on the configured property value [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 2 - --- 2020-09-10 Alistair Francis New
[PULL,04/30] hw/riscv: hart: Add a new 'resetvec' property [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 2 - --- 2020-09-10 Alistair Francis New
[PULL,03/30] target/riscv: cpu: Add a new 'resetvec' property [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 2 - --- 2020-09-10 Alistair Francis New
[PULL,02/30] riscv: sifive_test: Allow 16-bit writes to memory region [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap 1 2 1 - --- 2020-09-10 Alistair Francis New
[PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New