Show patches with: Submitter = Palmer Dabbelt       |    State = Action Required       |    Archived = No       |   530 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v7,28/35] target/riscv: Rename trans_arith to gen_arith target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,27/35] target/riscv: Remove manual decoding of RV32/64M insn target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,26/35] target/riscv: Remove shift and slt insn manual decoding target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,23/35] target/riscv: Remove manual decoding from gen_store() target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,22/35] target/riscv: Remove manual decoding from gen_load() target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,21/35] target/riscv: Remove manual decoding from gen_branch() target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,20/35] target/riscv: Remove gen_jalr() target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree target/riscv: Convert to decodetree - - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,16/35] target/riscv: Convert RV priv insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,15/35] target/riscv: Convert RV64D insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,14/35] target/riscv: Convert RV32D insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,13/35] target/riscv: Convert RV64F insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,12/35] target/riscv: Convert RV32F insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,11/35] target/riscv: Convert RV64A insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,10/35] target/riscv: Convert RV32A insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,09/35] target/riscv: Convert RVXM insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,08/35] target/riscv: Convert RVXI csr insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,07/35] target/riscv: Convert RVXI fence insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,06/35] target/riscv: Convert RVXI arithmetic insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,05/35] target/riscv: Convert RV64I load/store insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,04/35] target/riscv: Convert RV32I load/store insns to decodetree target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,03/35] target/riscv: Convert RVXI branch insns to decodetree target/riscv: Convert to decodetree 1 - 2 - --- 2019-02-13 Palmer Dabbelt New
[v7,02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC target/riscv: Convert to decodetree 1 - 1 - --- 2019-02-13 Palmer Dabbelt New
[v7,01/35] target/riscv: Move CPURISCVState pointer to DisasContext target/riscv: Convert to decodetree - - 3 - --- 2019-02-13 Palmer Dabbelt New
[PULL,11/11] riscv: Ensure the kernel start address is correctly cast Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,10/11] target/riscv: fix counter-enable checks in ctr() Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,09/11] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer Untitled series #91747 - - - - --- 2019-02-13 Palmer Dabbelt New
[PULL,08/11] RISC-V: Add misa runtime write support Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,07/11] RISC-V: Add misa.MAFD checks to translate Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,06/11] RISC-V: Add misa to DisasContext Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,05/11] RISC-V: Add priv_ver to DisasContext Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,04/11] RISC-V: Use riscv prefix consistently on cpu helpers Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,03/11] RISC-V: Implement mstatus.TSR/TW/TVM Untitled series #91747 - - - - --- 2019-02-13 Palmer Dabbelt New
[PULL,02/11] RISC-V: Mark mstatus.fs dirty Untitled series #91747 - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL,01/11] RISC-V: Split out mstatus_fs from tb_flags [PULL,01/11] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-13 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.0 Soft Freeze, Part 1 [PULL] RISC-V Patches for the 4.0 Soft Freeze, Part 1 - - - - --- 2019-02-13 Palmer Dabbelt New
[PULL,10/10] target/riscv: fix counter-enable checks in ctr() [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,09/10] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - - - --- 2019-02-02 Palmer Dabbelt New
[PULL,08/10] RISC-V: Add misa runtime write support [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,07/10] RISC-V: Add misa.MAFD checks to translate [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,06/10] RISC-V: Add misa to DisasContext [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,05/10] RISC-V: Add priv_ver to DisasContext [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,04/10] RISC-V: Use riscv prefix consistently on cpu helpers [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,03/10] RISC-V: Implement mstatus.TSR/TW/TVM [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - - - --- 2019-02-02 Palmer Dabbelt New
[PULL,02/10] RISC-V: Mark mstatus.fs dirty [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-02-02 Palmer Dabbelt New
[PULL] RISC-V Patches for 3.2, Part 3 [PULL] RISC-V Patches for 3.2, Part 3 - - - - --- 2019-02-02 Palmer Dabbelt New
[PULL,10/10] target/riscv: fix counter-enable checks in ctr() [PR,RFC] RISC-V Patches for 3.2, Part 3 - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PULL,09/10] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer [PR,RFC] RISC-V Patches for 3.2, Part 3 - - - - --- 2019-01-30 Palmer Dabbelt New
[PULL,08/10] RISC-V: Add misa runtime write support [PR,RFC] RISC-V Patches for 3.2, Part 3 - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PULL,07/10] RISC-V: Add misa.MAFD checks to translate [PR,RFC] RISC-V Patches for 3.2, Part 3 - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PULL,06/10] RISC-V: Add misa to DisasContext [PR,RFC] RISC-V Patches for 3.2, Part 3 - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PULL,05/10] RISC-V: Add priv_ver to DisasContext [PR,RFC] RISC-V Patches for 3.2, Part 3 - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PULL,04/10] RISC-V: Use riscv prefix consistently on cpu helpers [PR,RFC] RISC-V Patches for 3.2, Part 3 - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PULL,03/10] RISC-V: Implement mstatus.TSR/TW/TVM [PR,RFC] RISC-V Patches for 3.2, Part 3 - - - - --- 2019-01-30 Palmer Dabbelt New
[PULL,02/10] RISC-V: Mark mstatus.fs dirty [PR,RFC] RISC-V Patches for 3.2, Part 3 - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags [PULL,01/10] RISC-V: Split out mstatus_fs from tb_flags - - 1 - --- 2019-01-30 Palmer Dabbelt New
[PR,RFC] RISC-V Patches for 3.2, Part 3 [PR,RFC] RISC-V Patches for 3.2, Part 3 - - - - --- 2019-01-30 Palmer Dabbelt New
MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer - - - - --- 2019-01-25 Palmer Dabbelt New
[PULL,4/4] default-configs: Enable USB support for RISC-V machines [PULL] RISC-V Updates for 3.2, Part 2 - - - - --- 2019-01-11 Palmer Dabbelt New
[PULL,3/4] RISC-V: Implement existential predicates for CSRs [PULL] RISC-V Updates for 3.2, Part 2 - - 1 - --- 2019-01-11 Palmer Dabbelt New
[PULL,2/4] RISC-V: Implement atomic mip/sip CSR updates [PULL] RISC-V Updates for 3.2, Part 2 - - 1 - --- 2019-01-11 Palmer Dabbelt New
[PULL,1/4] RISC-V: Implement modular CSR helper interface [PULL,1/4] RISC-V: Implement modular CSR helper interface - - 1 - --- 2019-01-11 Palmer Dabbelt New
[PULL] RISC-V Updates for 3.2, Part 2 [PULL] RISC-V Updates for 3.2, Part 2 - - - - --- 2019-01-11 Palmer Dabbelt New
[PULL,14/14] MAINTAINERS: Mark RISC-V as Supported [PULL] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,13/14] riscv/cpu: use device_class_set_parent_realize [PULL] RISC-V Changes for 3.2, Part 1 - - 2 - --- 2018-12-26 Palmer Dabbelt New
[PULL,12/14] target/riscv/pmp.c: Fix pmp_decode_napot() [PULL] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,11/14] sifive_uart: Implement interrupt pending register [PULL] RISC-V Changes for 3.2, Part 1 - - 2 - --- 2018-12-26 Palmer Dabbelt New
[PULL,10/14] RISC-V: Enable second UART on sifive_e and sifive_u [PULL] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,09/14] RISC-V: Fix PLIC pending bitfield reads [PULL] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,08/14] RISC-V: Fix CLINT timecmp low 32-bit writes [PULL] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,07/14] RISC-V: Add hartid and \n to interrupt logging [PULL] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART [PULL] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,05/14] sifive_u: Add clock DT node for GEM ethernet [PULL] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,04/14] riscv: Enable VGA and PCIE_VGA [PULL] RISC-V Changes for 3.2, Part 1 - - 1 1 --- 2018-12-26 Palmer Dabbelt New
[PULL,03/14] hw/riscv/virt: Connect the gpex PCIe [PULL] RISC-V Changes for 3.2, Part 1 - - 1 2 --- 2018-12-26 Palmer Dabbelt New
[PULL,02/14] hw/riscv/virt: Adjust memory layout spacing [PULL] RISC-V Changes for 3.2, Part 1 - - 1 2 --- 2018-12-26 Palmer Dabbelt New
[PULL,01/14] hw/riscv/virt: Increase the number of interrupts [PULL,01/14] hw/riscv/virt: Increase the number of interrupts - - - 2 --- 2018-12-26 Palmer Dabbelt New
[PULL] RISC-V Changes for 3.2, Part 1 [PULL] RISC-V Changes for 3.2, Part 1 - - - - --- 2018-12-26 Palmer Dabbelt New
[PULL,14/14] MAINTAINERS: Mark RISC-V as Supported [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-21 Palmer Dabbelt New
[PULL,13/14] riscv/cpu: use device_class_set_parent_realize [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 2 - --- 2018-12-21 Palmer Dabbelt New
[PULL,12/14] target/riscv/pmp.c: Fix pmp_decode_napot() [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-21 Palmer Dabbelt New
[PULL,11/14] sifive_uart: Implement interrupt pending register [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 2 - --- 2018-12-21 Palmer Dabbelt New
[PULL,10/14] RISC-V: Enable second UART on sifive_e and sifive_u [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-21 Palmer Dabbelt New
[PULL,09/14] RISC-V: Fix PLIC pending bitfield reads [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-21 Palmer Dabbelt New
[PULL,08/14] RISC-V: Fix CLINT timecmp low 32-bit writes [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-21 Palmer Dabbelt New
[PULL,07/14] RISC-V: Add hartid and \n to interrupt logging [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-21 Palmer Dabbelt New
[PULL,06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-21 Palmer Dabbelt New
[PULL,05/14] sifive_u: Add clock DT node for GEM ethernet [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 1 - --- 2018-12-21 Palmer Dabbelt New
[PULL,04/14] riscv: Enable VGA and PCIE_VGA [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 1 1 --- 2018-12-21 Palmer Dabbelt New
[PULL,03/14] hw/riscv/virt: Connect the gpex PCIe [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 1 2 --- 2018-12-21 Palmer Dabbelt New
[PULL,02/14] hw/riscv/virt: Adjust memory layout spacing [PR,RFC] RISC-V Changes for 3.2, Part 1 - - 1 2 --- 2018-12-21 Palmer Dabbelt New
[PULL,01/14] hw/riscv/virt: Increase the number of interrupts [PULL,01/14] hw/riscv/virt: Increase the number of interrupts - - - 2 --- 2018-12-21 Palmer Dabbelt New
[PR,RFC] RISC-V Changes for 3.2, Part 1 [PR,RFC] RISC-V Changes for 3.2, Part 1 - - - - --- 2018-12-21 Palmer Dabbelt New
[for-3.1,2/2] MAINTAINERS: Mark RISC-V as Supported Untitled series #77367 - - 1 - --- 2018-11-21 Palmer Dabbelt New
[for-3.1,1/2] MAINTAINERS: Any file with "riscv" in the name is a RISC-V file [for-3.1,1/2] MAINTAINERS: Any file with "riscv" in the name is a RISC-V file - - - - --- 2018-11-21 Palmer Dabbelt New
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