Show patches with: Submitter = Palmer Dabbelt       |    State = Action Required       |    Archived = No       |   530 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,29/34] riscv: sifive_u: Update the plic hart config to support multicore [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,28/34] riscv: sifive_u: Do not create hard-coded phandles in DT [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,27/34] disas/riscv: Fix `rdinstreth` constraint [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,26/34] disas/riscv: Disassemble reserved compressed encodings as illegal [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,25/34] riscv: virt: Add cpu-topology DT node. [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,24/34] RISC-V: Update syscall list for 32-bit support. [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,23/34] RISC-V: Clear load reservations on context switch and SC [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 2 - --- 2019-06-27 Palmer Dabbelt New
[PULL,22/34] RISC-V: Add support for the Zicsr extension [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,21/34] RISC-V: Add support for the Zifencei extension [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,20/34] target/riscv: Add support for disabling/enabling Counters [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,19/34] target/riscv: Remove user version information [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,18/34] target/riscv: Require either I or E base extension [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - - - --- 2019-06-27 Palmer Dabbelt New
[PULL,16/34] target/riscv: Set privledge spec 1.11.0 as default [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,15/34] target/riscv: Add the mcountinhibit CSR [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,14/34] target/riscv: Add the privledge spec version 1.11.0 [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,13/34] target/riscv: Restructure deprecatd CPUs [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,12/34] RISC-V: Fix a memory leak when realizing a sifive_e [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - 1 2 - --- 2019-06-27 Palmer Dabbelt New
[PULL,11/34] riscv: virt: Correct pci "bus-range" encoding [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,10/34] RISC-V: Fix a PMP check with the correct access size [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,08/34] RISC-V: Check PMP during Page Table Walks [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,07/34] RISC-V: Check for the effective memory privilege mode during PMP checks [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,06/34] RISC-V: Raise access fault exceptions on PMP violations [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,05/34] RISC-V: Only Check PMP if MMU translation succeeds [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,04/34] target/riscv: Implement riscv_cpu_unassigned_access [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,03/34] target/riscv: Fix PMP range boundary address bug [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 2 - --- 2019-06-27 Palmer Dabbelt New
[PULL,02/34] sifive_prci: Read and write PRCI registers [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - - - - --- 2019-06-27 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - - - - --- 2019-06-27 Palmer Dabbelt New
RISC-V: Add support for the Zicsr extension RISC-V: Add support for the Zicsr extension - - 1 - --- 2019-06-25 Palmer Dabbelt New
RISC-V: Add support for the Zifencei extension RISC-V: Add support for the Zifencei extension - - - - --- 2019-06-25 Palmer Dabbelt New
RISC-V: Fix a memory leak when realizing a sifive_e RISC-V: Fix a memory leak when realizing a sifive_e - 1 2 - --- 2019-06-14 Palmer Dabbelt New
sifive_prci: Read and write PRCI registers sifive_prci: Read and write PRCI registers - - 1 - --- 2019-05-29 Palmer Dabbelt New
[PULL,29/29] target/riscv: Only flush TLB if SATP.ASID changes [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,28/29] target/riscv: More accurate handling of `sip` CSR [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,27/29] target/riscv: Add checks for several RVC reserved operands [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,26/29] target/riscv: Add the HGATP register masks [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,25/29] target/riscv: Add the HSTATUS register masks [PULL,01/29] SiFive RISC-V GPIO Device - - - - --- 2019-05-26 Palmer Dabbelt New
[PULL,24/29] target/riscv: Add Hypervisor CSR macros [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,23/29] target/riscv: Allow setting mstatus virtulisation bits [PULL,01/29] SiFive RISC-V GPIO Device - - - - --- 2019-05-26 Palmer Dabbelt New
[PULL,22/29] target/riscv: Add the MPV and MTL mstatus bits [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,21/29] target/riscv: Improve the scause logic [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,20/29] target/riscv: Trigger interrupt on MIP update asynchronously [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,19/29] target/riscv: Mark privilege level 2 as reserved [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,18/29] riscv: spike: Add a generic spike machine [PULL,01/29] SiFive RISC-V GPIO Device 1 - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,17/29] target/riscv: Deprecate the generic no MMU CPUs [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,16/29] target/riscv: Add a base 32 and 64 bit CPU [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,15/29] target/riscv: Create settable CPU properties [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,14/29] riscv: virt: Allow specifying a CPU via commandline [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,13/29] linux-user/riscv: Add the CPU type as a comment [PULL,01/29] SiFive RISC-V GPIO Device - - - - --- 2019-05-26 Palmer Dabbelt New
[PULL,12/29] target/riscv: Remove unused include of riscv_htif.h for virt board riscv [PULL,01/29] SiFive RISC-V GPIO Device - - 2 - --- 2019-05-26 Palmer Dabbelt New
[PULL,11/29] target/riscv: Remove spaces from register names [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,10/29] target/riscv: Split gen_arith_imm into functional and temp [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,09/29] target/riscv: Split RVC32 and RVC64 insns into separate files [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,08/29] target/riscv: Use pattern groups in insn16.decode [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,07/29] target/riscv: Merge argument decode for RVC shifti [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,06/29] target/riscv: Merge argument sets for insn32 and insn16 [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,05/29] target/riscv: Use --static-decode for decodetree [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,04/29] target/riscv: Name the argument sets for all of insn32 formats [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,03/29] RISC-V: fix single stepping over ret and other branching instructions [PULL,01/29] SiFive RISC-V GPIO Device - - 2 - --- 2019-05-26 Palmer Dabbelt New
[PULL,02/29] target/riscv: Do not allow sfence.vma from user mode [PULL,01/29] SiFive RISC-V GPIO Device - - 2 - --- 2019-05-26 Palmer Dabbelt New
[PULL,01/29] SiFive RISC-V GPIO Device [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1 [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1 - - - - --- 2019-05-26 Palmer Dabbelt New
[PULL,2/2] riscv: plic: Log guest errors [PULL] RISC-V Patches for 4.0-rc3, v2 - - - - --- 2019-04-05 Palmer Dabbelt New
[PULL,1/2] riscv: plic: Fix incorrect irq calculation [PULL,1/2] riscv: plic: Fix incorrect irq calculation - - - - --- 2019-04-05 Palmer Dabbelt New
[PULL] RISC-V Patches for 4.0-rc3, v2 [PULL] RISC-V Patches for 4.0-rc3, v2 - - - - --- 2019-04-05 Palmer Dabbelt New
[PULL,2/2] riscv: plic: Log guest errors Untitled series #100904 - - 2 - --- 2019-04-04 Palmer Dabbelt New
[PULL,1/2] riscv: plic: Fix incorrect irq calculation [PULL,1/2] riscv: plic: Fix incorrect irq calculation - - 1 - --- 2019-04-04 Palmer Dabbelt New
[PULL] RISC-V Patches for 4.0-rc3 [PULL] RISC-V Patches for 4.0-rc3 - - - - --- 2019-04-04 Palmer Dabbelt New
[PULL] target/riscv: Fix wrong expanding for c.fswsp [PULL] target/riscv: Fix wrong expanding for c.fswsp - - 1 - --- 2019-03-26 Palmer Dabbelt New
[PULL] A second RISC-V Patch for 4.0.0-rc1 [PULL] A second RISC-V Patch for 4.0.0-rc1 - - - - --- 2019-03-26 Palmer Dabbelt New
[PULL] target/riscv: Zero extend the inputs of divuw and remuw [PULL] target/riscv: Zero extend the inputs of divuw and remuw - - 1 - --- 2019-03-26 Palmer Dabbelt New
[PULL] A Single RISC-V Patch for 4.0-rc1 [PULL] A Single RISC-V Patch for 4.0-rc1 - - - - --- 2019-03-26 Palmer Dabbelt New
sifive_prci: Read and write PRCI registers sifive_prci: Read and write PRCI registers - - 2 - --- 2019-03-22 Palmer Dabbelt New
target/riscv: Zero extend the inputs of divuw and remuw target/riscv: Zero extend the inputs of divuw and remuw - - 1 - --- 2019-03-21 Palmer Dabbelt New
[PULL,19/19] riscv: sifive_u: Correct UART0's IRQ in the device tree [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - 1 - --- 2019-03-19 Palmer Dabbelt New
[PULL,18/19] riscv: sifive_uart: Generate TX interrupt [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - 1 - --- 2019-03-19 Palmer Dabbelt New
[PULL,17/19] target/riscv: Remove unused struct [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - - - --- 2019-03-19 Palmer Dabbelt New
[PULL,16/19] riscv: sifive_u: Allow up to 4 CPUs to be created [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - - - --- 2019-03-19 Palmer Dabbelt New
[PULL,15/19] RISC-V: Update load reservation comment in do_interrupt [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - - - --- 2019-03-19 Palmer Dabbelt New
[PULL,14/19] RISC-V: Convert trap debugging to trace events [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - - - --- 2019-03-19 Palmer Dabbelt New
[PULL,13/19] RISC-V: Add support for vectored interrupts [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - - - --- 2019-03-19 Palmer Dabbelt New
[PULL,12/19] RISC-V: Change local interrupts from edge to level [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - - - --- 2019-03-19 Palmer Dabbelt New
[PULL,11/19] RISC-V: linux-user support for RVE ABI [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - - - --- 2019-03-19 Palmer Dabbelt New
[PULL,10/19] elf: Add RISC-V PSABI ELF header defines [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - 1 - --- 2019-03-19 Palmer Dabbelt New
[PULL,09/19] RISC-V: Remove unnecessary disassembler constraints [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - - - --- 2019-03-19 Palmer Dabbelt New
[PULL,08/19] RISC-V: Allow interrupt controllers to claim interrupts [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - - - --- 2019-03-19 Palmer Dabbelt New
[PULL,07/19] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - - - --- 2019-03-19 Palmer Dabbelt New
[PULL,06/19] riscv: pmp: Log pmp access errors as guest errors [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - - - --- 2019-03-19 Palmer Dabbelt New
[PULL,05/19] RISC-V: Add hooks to use the gdb xml files. [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - 1 - --- 2019-03-19 Palmer Dabbelt New
[PULL,04/19] RISC-V: Add debug support for accessing CSRs. [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - 1 - --- 2019-03-19 Palmer Dabbelt New
[PULL,03/19] RISC-V: Fixes to CSR_* register macros. [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - 1 - --- 2019-03-19 Palmer Dabbelt New
[PULL,02/19] RISC-V: Add 64-bit gdb xml files. [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - 1 - --- 2019-03-19 Palmer Dabbelt New
[PULL,01/19] RISC-V: Add 32-bit gdb xml files. [PULL,01/19] RISC-V: Add 32-bit gdb xml files. - - 1 - --- 2019-03-19 Palmer Dabbelt New
[PULL] RISC-V Patches for 4.0-rc0, Part 2 [PULL] RISC-V Patches for 4.0-rc0, Part 2 - - - - --- 2019-03-19 Palmer Dabbelt New
[PULL] target/riscv: Fix manually parsed 16 bit insn [PULL] target/riscv: Fix manually parsed 16 bit insn - - 1 2 --- 2019-03-18 Palmer Dabbelt New
[PULL] A Single RISC-V Patch for 4.0-rc0 [PULL] A Single RISC-V Patch for 4.0-rc0 - - - - --- 2019-03-18 Palmer Dabbelt New
[PULL,29/29] target/riscv: Remove decode_RV32_64G() [PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC - - 1 - --- 2019-03-13 Palmer Dabbelt New
[PULL,28/29] target/riscv: Remove gen_system() [PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC - - 1 - --- 2019-03-13 Palmer Dabbelt New
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