diff mbox series

[v7,01/35] target/riscv: Move CPURISCVState pointer to DisasContext

Message ID 20190213155414.22285-2-palmer@sifive.com
State New
Headers show
Series target/riscv: Convert to decodetree | expand

Commit Message

Palmer Dabbelt Feb. 13, 2019, 3:53 p.m. UTC 
From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

CPURISCVState is rarely used, so there is no need to pass it to every
translate function. This paves the way for decodetree which only passes
DisasContext to translate functions.

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target/riscv/translate.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Comments

Bastian Koppelmann Feb. 13, 2019, 4:18 p.m. UTC | #1 
On 2/13/19 4:53 PM, Palmer Dabbelt wrote:
> From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
>
> CPURISCVState is rarely used, so there is no need to pass it to every
> translate function. This paves the way for decodetree which only passes
> DisasContext to translate functions.
>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
>   target/riscv/translate.c | 7 ++++---
>   1 file changed, 4 insertions(+), 3 deletions(-)

We can drop this patch as you pull request already fixes this. (see 
https://patchwork.kernel.org/patch/10794241/)

Cheers,

Bastian
diff mbox series

Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b7176cbf98e1..9e06eb8c2de5 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -54,6 +54,7 @@  typedef struct DisasContext {
        to any system register, which includes CSR_FRM, so we do not have
        to reset this known value.  */
     int frm;
+    CPURISCVState *env;
 } DisasContext;
 
 /* convert riscv funct3 to qemu memop for load/store */
@@ -2003,7 +2004,7 @@  static void decode_opc(DisasContext *ctx)
 {
     /* check for compressed insn */
     if (extract32(ctx->opcode, 0, 2) != 3) {
-        if (!has_ext(ctx, RVC)) {
+        if (!riscv_has_ext(ctx->env, RVC)) {
             gen_exception_illegal(ctx);
         } else {
             ctx->pc_succ_insn = ctx->base.pc_next + 2;
@@ -2058,9 +2059,9 @@  static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
-    CPURISCVState *env = cpu->env_ptr;
+    ctx->env = cpu->env_ptr;
 
-    ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
+    ctx->opcode = cpu_ldl_code(ctx->env, ctx->base.pc_next);
     decode_opc(ctx);
     ctx->base.pc_next = ctx->pc_succ_insn;