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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[v10,25/61] target/riscv: vector single-width averaging add and subtract
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,24/61] target/riscv: vector single-width saturating add and subtract
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,23/61] target/riscv: vector integer merge and move instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,22/61] target/riscv: vector widening integer multiply-add instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,21/61] target/riscv: vector single-width integer multiply-add instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,20/61] target/riscv: vector widening integer multiply instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,19/61] target/riscv: vector integer divide instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,18/61] target/riscv: vector single-width integer multiply instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,17/61] target/riscv: vector integer min/max instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,16/61] target/riscv: vector integer comparison instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,15/61] target/riscv: vector narrowing integer right shift instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,14/61] target/riscv: vector single-width bit shift instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,13/61] target/riscv: vector bitwise logical instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,11/61] target/riscv: vector widening integer add and subtract
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,10/61] target/riscv: vector single-width integer add and subtract
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,09/61] target/riscv: add vector amo operations
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,08/61] target/riscv: add fault-only-first unit stride load
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,07/61] target/riscv: add vector index load and store instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,06/61] target/riscv: add vector stride load and store instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,05/61] target/riscv: add an internals.h header
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,04/61] target/riscv: add vector configure instruction
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,03/61] target/riscv: support vector extension csr
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,02/61] target/riscv: implementation-defined constant parameters
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,01/61] target/riscv: add vector extension field in CPURISCVState
target/riscv: support vector extension v0.7.1
1 - 1 -
-
-
-
2020-06-20
LIU Zhiwei
New
target/s390x: Fix SQXBR
target/s390x: Fix SQXBR
- - 1 -
-
-
-
2020-06-20
Richard Henderson
New
[v10,37/61] target/riscv: vector floating-point min/max instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,36/61] target/riscv: vector floating-point square-root instruction
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,35/61] target/riscv: vector widening floating-point fused multiply-add instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,34/61] target/riscv: vector single-width floating-point fused multiply-add instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,33/61] target/riscv: vector widening floating-point multiply
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,32/61] target/riscv: vector single-width floating-point multiply/divide instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,31/61] target/riscv: vector widening floating-point add/subtract instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,30/61] target/riscv: vector single-width floating-point add/subtract instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,29/61] target/riscv: vector narrowing fixed-point clip instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,28/61] target/riscv: vector single-width scaling shift instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,27/61] target/riscv: vector widening saturating scaled multiply-add
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,26/61] target/riscv: vector single-width fractional multiply with rounding and saturation
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,25/61] target/riscv: vector single-width averaging add and subtract
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,24/61] target/riscv: vector single-width saturating add and subtract
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,23/61] target/riscv: vector integer merge and move instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,22/61] target/riscv: vector widening integer multiply-add instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,21/61] target/riscv: vector single-width integer multiply-add instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,20/61] target/riscv: vector widening integer multiply instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,19/61] target/riscv: vector integer divide instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,18/61] target/riscv: vector single-width integer multiply instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,17/61] target/riscv: vector integer min/max instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,16/61] target/riscv: vector integer comparison instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,15/61] target/riscv: vector narrowing integer right shift instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,14/61] target/riscv: vector single-width bit shift instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,13/61] target/riscv: vector bitwise logical instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,11/61] target/riscv: vector widening integer add and subtract
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,10/61] target/riscv: vector single-width integer add and subtract
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,09/61] target/riscv: add vector amo operations
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,08/61] target/riscv: add fault-only-first unit stride load
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,07/61] target/riscv: add vector index load and store instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,06/61] target/riscv: add vector stride load and store instructions
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,05/61] target/riscv: add an internals.h header
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,04/61] target/riscv: add vector configure instruction
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,03/61] target/riscv: support vector extension csr
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,02/61] target/riscv: implementation-defined constant parameters
target/riscv: support vector extension v0.7.1
- - 2 -
-
-
-
2020-06-20
LIU Zhiwei
New
[v10,01/61] target/riscv: add vector extension field in CPURISCVState
target/riscv: support vector extension v0.7.1
1 - 1 -
-
-
-
2020-06-20
LIU Zhiwei
New
[2/2] virtio-balloon: Replace free page hinting references to 'report' with 'hint'
virtio-balloon: Free page hinting clean-ups
1 - - -
-
-
-
2020-06-19
Alexander H Duyck
New
[1/2] virtio-balloon: Prevent guest from starting a report when we didn't request one
virtio-balloon: Free page hinting clean-ups
1 1 - -
-
-
-
2020-06-19
Alexander H Duyck
New
target/i386: reimplement fpatan using floatx80 operations
target/i386: reimplement fpatan using floatx80 operations
- - - -
-
-
-
2020-06-19
Joseph Myers
New
[v3,6/6] bitmaps: Use x- prefix for block-dirty-bitmap-popluate
block: add block-dirty-bitmap-populate job
- - - -
-
-
-
2020-06-19
Eric Blake
New
[v3,5/6] iotests: add 298 for block-dirty-bitmap-populate
block: add block-dirty-bitmap-populate job
- - - -
-
-
-
2020-06-19
Eric Blake
New
[v3,4/6] iotests: move bitmap helpers into their own file
block: add block-dirty-bitmap-populate job
- - 1 -
-
-
-
2020-06-19
Eric Blake
New
[v3,3/6] qmp: expose block-dirty-bitmap-populate
block: add block-dirty-bitmap-populate job
- - - -
-
-
-
2020-06-19
Eric Blake
New
[v3,2/6] blockdev: combine DriveBackupState and BlockdevBackupState
block: add block-dirty-bitmap-populate job
- - - -
-
-
-
2020-06-19
Eric Blake
New
[v3,1/6] block: add bitmap-populate job
block: add block-dirty-bitmap-populate job
- - - -
-
-
-
2020-06-19
Eric Blake
New
virtiofsd: Allow capability restriction to be turned off
virtiofsd: Allow capability restriction to be turned off
- - - -
-
-
-
2020-06-19
Dr. David Alan Gilbert
New
target/arm: Remove dead code relating to SABA and UABA
target/arm: Remove dead code relating to SABA and UABA
- 1 2 -
-
-
-
2020-06-19
Peter Maydell
New
[v2] docs/devel: add some notes on tcg-icount for developers
[v2] docs/devel: add some notes on tcg-icount for developers
- - 1 -
-
-
-
2020-06-19
Alex Bennée
New
target/arm: Remove unnecessary gen_io_end() calls
target/arm: Remove unnecessary gen_io_end() calls
- - 3 -
-
-
-
2020-06-19
Peter Maydell
New
[PULL,v2,32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
-
-
-
2020-06-19
Alistair Francis
New
[PULL,v2,31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
-
-
-
2020-06-19
Alistair Francis
New
[PULL,v2,30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
-
-
-
2020-06-19
Alistair Francis
New
[PULL,v2,29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
-
-
-
2020-06-19
Alistair Francis
New
[PULL,v2,28/32] target/riscv: Rename IBEX CPU init routine
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
-
-
-
2020-06-19
Alistair Francis
New
[PULL,v2,27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
-
-
-
2020-06-19
Alistair Francis
New
[PULL,v2,26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
-
-
-
2020-06-19
Alistair Francis
New
[PULL,v2,25/32] hw/riscv: sifive_u: Add reset functionality
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
-
-
-
2020-06-19
Alistair Francis
New
[PULL,v2,24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
-
-
-
2020-06-19
Alistair Francis
New
[PULL,v2,23/32] hw/riscv: sifive_u: Hook a GPIO controller
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
-
-
-
2020-06-19
Alistair Francis
New
[PULL,v2,22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
-
-
-
2020-06-19
Alistair Francis
New
[PULL,v2,21/32] hw/riscv: sifive_gpio: Clean up the codes
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
-
-
-
2020-06-19
Alistair Francis
New
[PULL,v2,20/32] hw/riscv: sifive_u: Generate device tree node for OTP
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,v2,19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,v2,18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,v2,17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
-
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2020-06-19
Alistair Francis
New
[PULL,v2,16/32] target/riscv: Use a smaller guess size for no-MMU PMP
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,v2,15/32] riscv/opentitan: Connect the UART device
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 2 -
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2020-06-19
Alistair Francis
New
[PULL,v2,14/32] riscv/opentitan: Connect the PLIC device
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 2 -
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2020-06-19
Alistair Francis
New
[PULL,v2,13/32] hw/intc: Initial commit of lowRISC Ibex PLIC
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,v2,12/32] hw/char: Initial commit of Ibex UART
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,v2,11/32] riscv/opentitan: Fix the ROM size
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - - -
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2020-06-19
Alistair Francis
New
[PULL,v2,10/32] target/riscv: Implement checks for hfence
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
-
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2020-06-19
Alistair Francis
New
[PULL,v2,09/32] target/riscv: Move the hfence instructions to the rvh decode
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
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