Show patches with: Submitter = LIU Zhiwei       |    State = Action Required       |    Archived = No       |   783 patches
« 1 2 3 47 8 »
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[38/38] target/riscv: configure and turn on packed extension from command line target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[37/38] target/riscv: RV64 Only 32-bit Packing Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[35/38] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[33/38] target/riscv: RV64 Only 32-bit Multiply Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[28/38] target/riscv: Non-SIMD Miscellaneous Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[27/38] target/riscv: 32-bit Computation Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[26/38] target/riscv: Non-SIMD Q31 saturation ALU Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[24/38] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[23/38] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[22/38] target/riscv: 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[20/38] target/riscv: Partial-SIMD Miscellaneous Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[19/38] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[17/38] target/riscv: Signed MSW 32x16 Multiply and Add Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[15/38] target/riscv: 16-bit Packing Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[14/38] target/riscv: 8-bit Unpacking Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[13/38] target/riscv: SIMD 8-bit Miscellaneous Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[11/38] target/riscv: SIMD 8-bit Multiply Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[10/38] target/riscv: SIMD 16-bit Multiply Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[09/38] target/riscv: SIMD 8-bit Compare Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[08/38] target/riscv: SIMD 16-bit Compare Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[07/38] target/riscv: SIMD 8-bit Shift Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[06/38] target/riscv: SIMD 16-bit Shift Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[05/38] target/riscv: 8-bit Addition & Subtraction Instruction target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[04/38] target/riscv: 16-bit Addition & Subtraction Instructions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[03/38] target/riscv: Fixup saturate subtract function target/riscv: support packed extension v0.9.2 - - 1 - --- 2021-02-12 LIU Zhiwei New
[02/38] target/riscv: Hoist vector functions target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[01/38] target/riscv: implementation-defined constant parameters target/riscv: support packed extension v0.9.2 - - - - --- 2021-02-12 LIU Zhiwei New
[4/4] target/arm: adjust CPTR_EL2 according to HCR_EL2.E2H target/arm bug fix - - 1 - --- 2020-12-07 LIU Zhiwei New
[3/4] target/arm: Fixup SIMD fcmla(by element) in 4H arrangement target/arm bug fix - - - - --- 2020-12-07 LIU Zhiwei New
[2/4] target/arm: Fixup contiguous first-fault and no-fault loads target/arm bug fix - - - - --- 2020-12-07 LIU Zhiwei New
[1/4] target/arm: Fixup special cross page case for sve continuous load/store target/arm bug fix - - - - --- 2020-12-07 LIU Zhiwei New
[3/3] fpu/softfloat: Define misc operations for bfloat16 Implement blfoat16 in softfloat - - 1 - --- 2020-08-13 LIU Zhiwei New
[2/3] fpu/softfloat: Define convert operations for bfloat16 Implement blfoat16 in softfloat - - 1 - --- 2020-08-13 LIU Zhiwei New
[1/3] fpu/softfloat: Define operations for bfloat16 Implement blfoat16 in softfloat - - 1 - --- 2020-08-13 LIU Zhiwei New
[1/1] target/arm: adjust CPTR_EL2 according to HCR_EL2.E2H [1/1] target/arm: adjust CPTR_EL2 according to HCR_EL2.E2H - - 1 - --- 2020-08-11 LIU Zhiwei New
[2/2] target/riscv: fix vector index load/store constraints [1/2] target/riscv: Quiet Coverity complains about vamo* - - 1 - --- 2020-07-21 LIU Zhiwei New
[1/2] target/riscv: Quiet Coverity complains about vamo* [1/2] target/riscv: Quiet Coverity complains about vamo* - - 1 - --- 2020-07-21 LIU Zhiwei New
[RFC,8/8] fpu/softfloat: define misc operation for bfloat16 Implement blfoat16 in softfloat - - 1 - --- 2020-07-12 LIU Zhiwei New
[RFC,7/8] fpu/softfloat: define covert operation for bfloat16 Implement blfoat16 in softfloat - - 1 - --- 2020-07-12 LIU Zhiwei New
[RFC,6/8] fpu/softfloat: define operation for bfloat16 Implement blfoat16 in softfloat - - 1 - --- 2020-07-12 LIU Zhiwei New
[RFC,5/8] fpu/softfloat: define brain floating-point types Implement blfoat16 in softfloat - - - - --- 2020-07-12 LIU Zhiwei New
[RFC,4/8] fpu/softfloat: add pack and unpack interfaces for bfloat16 Implement blfoat16 in softfloat - - - - --- 2020-07-12 LIU Zhiwei New
[RFC,3/8] fpu/softfloat: add FloatFmt for bfloat16 Implement blfoat16 in softfloat - - 1 - --- 2020-07-12 LIU Zhiwei New
[RFC,2/8] fpu/softfloat: use the similiar logic to recognize sNaN and qNaN Implement blfoat16 in softfloat - - - - --- 2020-07-12 LIU Zhiwei New
[RFC,1/8] fpu/softfloat: fix up float16 nan recognition Implement blfoat16 in softfloat - - 1 - --- 2020-07-12 LIU Zhiwei New
[11/11] riscv: Add configure script RISC-V risu porting - - - - --- 2020-07-11 LIU Zhiwei New
[10/11] riscv: Implement payload load interfaces RISC-V risu porting - - - - --- 2020-07-11 LIU Zhiwei New
[09/11] riscv: Define riscv struct reginfo RISC-V risu porting - - - - --- 2020-07-11 LIU Zhiwei New
[08/11] riscv: Add standard test case RISC-V risu porting - - 1 - --- 2020-07-11 LIU Zhiwei New
[07/11] riscv: Generate payload scripts RISC-V risu porting - - - - --- 2020-07-11 LIU Zhiwei New
[06/11] riscv: Add RV64C instructions description RISC-V risu porting - - - - --- 2020-07-11 LIU Zhiwei New
[05/11] riscv: Add RV64D instructions description RISC-V risu porting - - - - --- 2020-07-11 LIU Zhiwei New
[04/11] riscv: Add RV64F instructions description RISC-V risu porting - - - - --- 2020-07-11 LIU Zhiwei New
[03/11] riscv: Add RV64A instructions description RISC-V risu porting - - - - --- 2020-07-11 LIU Zhiwei New
[02/11] riscv: Add RV64M instructions description RISC-V risu porting - - - - --- 2020-07-11 LIU Zhiwei New
[01/11] riscv: Add RV64I instructions description RISC-V risu porting - - - - --- 2020-07-11 LIU Zhiwei New
[v12,61/61] target/riscv: configure and turn on vector extension from command line target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,60/61] target/riscv: vector compress instruction target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,59/61] target/riscv: vector register gather instruction target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,58/61] target/riscv: vector slide instructions target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,57/61] target/riscv: floating-point scalar move instructions target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,56/61] target/riscv: integer scalar move instruction target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,55/61] target/riscv: integer extract instruction target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,54/61] target/riscv: vector element index instruction target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,53/61] target/riscv: vector iota instruction target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,52/61] target/riscv: set-X-first mask bit target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,51/61] target/riscv: vmfirst find-first-set mask bit target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,50/61] target/riscv: vector mask population count vmpopc target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,49/61] target/riscv: vector mask-register logical instructions target/riscv: support vector extension v0.7.1 - - 1 - --- 2020-07-01 LIU Zhiwei New
[v12,48/61] target/riscv: vector widening floating-point reduction instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,47/61] target/riscv: vector single-width floating-point reduction instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,46/61] target/riscv: vector wideing integer reduction instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,45/61] target/riscv: vector single-width integer reduction instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,44/61] target/riscv: narrowing floating-point/integer type-convert instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,43/61] target/riscv: widening floating-point/integer type-convert instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,42/61] target/riscv: vector floating-point/integer type-convert instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,41/61] target/riscv: vector floating-point merge instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,40/61] target/riscv: vector floating-point classify instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,39/61] target/riscv: vector floating-point compare instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,38/61] target/riscv: vector floating-point sign-injection instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,37/61] target/riscv: vector floating-point min/max instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,36/61] target/riscv: vector floating-point square-root instruction target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,35/61] target/riscv: vector widening floating-point fused multiply-add instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,34/61] target/riscv: vector single-width floating-point fused multiply-add instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,33/61] target/riscv: vector widening floating-point multiply target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,32/61] target/riscv: vector single-width floating-point multiply/divide instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,31/61] target/riscv: vector widening floating-point add/subtract instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,30/61] target/riscv: vector single-width floating-point add/subtract instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
[v12,29/61] target/riscv: vector narrowing fixed-point clip instructions target/riscv: support vector extension v0.7.1 - - 2 - --- 2020-07-01 LIU Zhiwei New
« 1 2 3 47 8 »