Show patches with: Series = [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register       |    State = Action Required       |    Archived = No       |   32 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,v2,32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,28/32] target/riscv: Rename IBEX CPU init routine [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,25/32] hw/riscv: sifive_u: Add reset functionality [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,23/32] hw/riscv: sifive_u: Hook a GPIO controller [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,21/32] hw/riscv: sifive_gpio: Clean up the codes [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,20/32] hw/riscv: sifive_u: Generate device tree node for OTP [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,16/32] target/riscv: Use a smaller guess size for no-MMU PMP [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,15/32] riscv/opentitan: Connect the UART device [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 2 - --- 2020-06-19 Alistair Francis New
[PULL,v2,14/32] riscv/opentitan: Connect the PLIC device [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 2 - --- 2020-06-19 Alistair Francis New
[PULL,v2,13/32] hw/intc: Initial commit of lowRISC Ibex PLIC [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,12/32] hw/char: Initial commit of Ibex UART [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,11/32] riscv/opentitan: Fix the ROM size [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - - - --- 2020-06-19 Alistair Francis New
[PULL,v2,10/32] target/riscv: Implement checks for hfence [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,09/32] target/riscv: Move the hfence instructions to the rvh decode [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,08/32] target/riscv: Report errors validating 2nd-stage PTEs [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,07/32] target/riscv: Set access as data_load when validating stage-2 PTEs [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,06/32] riscv: Keep the CPU init routine names consistent [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,05/32] riscv: Generalize CPU init routine for the imacu CPU [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,04/32] riscv: Generalize CPU init routine for the gcsu CPU [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,03/32] riscv: Generalize CPU init routine for the base CPU [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,02/32] sifive_e: Support the revB machine [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - - - --- 2020-06-19 Alistair Francis New
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - 2 - --- 2020-06-19 Alistair Francis New