Show patches with: State = Action Required       |    Archived = No       |   127033 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
RISC-V: Normalize SEW = 64 handling into a simplified function RISC-V: Normalize SEW = 64 handling into a simplified function - - - - --- 2023-02-15 juzhe.zhong@rivai.ai New
RISC-V: Normalize arch string in driver time RISC-V: Normalize arch string in driver time - - - - --- 2020-06-19 Kito Cheng New
RISC-V: Normalize user vsetvl intrinsics[PR112092] RISC-V: Normalize user vsetvl intrinsics[PR112092] - - - - --- 2023-11-08 juzhe.zhong@rivai.ai New
RISC-V: Note that __builtin_riscv_pause() implies Xgnuzihintpausestate RISC-V: Note that __builtin_riscv_pause() implies Xgnuzihintpausestate - - - - --- 2022-11-18 Palmer Dabbelt New
RISC-V: Optimal RVV epilogue logic. RISC-V: Optimal RVV epilogue logic. - - - - --- 2022-11-14 Jiawei New
RISC-V: Optimise adding a (larger than simm12) constant RISC-V: Optimise adding a (larger than simm12) constant - - - - --- 2022-11-09 Philipp Tomsich New
RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451] RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451] - - - - --- 2023-09-22 Li Xu New
RISC-V: Optimize SELECT_VL codegen when length is known as smaller than VF RISC-V: Optimize SELECT_VL codegen when length is known as smaller than VF - - - - --- 2023-12-20 juzhe.zhong@rivai.ai New
RISC-V: Optimize TARGET_XTHEADCONDMOV RISC-V: Optimize TARGET_XTHEADCONDMOV - - - - --- 2023-05-26 Die Li New
RISC-V: Optimize VLA SLP with duplicate VLA shuffle indice RISC-V: Optimize VLA SLP with duplicate VLA shuffle indice - - - - --- 2023-11-17 juzhe.zhong@rivai.ai New
RISC-V: Optimize VSETVL codegen of SELECT_VL with LEN_MASK_{LOAD, STORE} RISC-V: Optimize VSETVL codegen of SELECT_VL with LEN_MASK_{LOAD, STORE} - - - - --- 2023-06-25 juzhe.zhong@rivai.ai New
RISC-V: Optimize a special case of VLA SLP RISC-V: Optimize a special case of VLA SLP - - - - --- 2023-11-23 juzhe.zhong@rivai.ai New
RISC-V: Optimize branches testing a bit-range or a shifted immediate RISC-V: Optimize branches testing a bit-range or a shifted immediate - - - - --- 2022-11-08 Philipp Tomsich New
RISC-V: Optimize codegen of VLA SLP RISC-V: Optimize codegen of VLA SLP - - - - --- 2023-06-20 juzhe.zhong@rivai.ai New
RISC-V: Optimize combine sequence by merge approach RISC-V: Optimize combine sequence by merge approach - - - - --- 2023-11-13 juzhe.zhong@rivai.ai New
RISC-V: Optimize consecutive permutation index pattern by vrgather.vi/vx RISC-V: Optimize consecutive permutation index pattern by vrgather.vi/vx - - - - --- 2023-10-18 juzhe.zhong@rivai.ai New
RISC-V: Optimize load memory data in rv64 RISC-V: Optimize load memory data in rv64 - - - - --- 2023-03-24 Feng Wang New
RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND - - - - --- 2022-11-10 Philipp Tomsich New
RISC-V: Optimize min/max with SImode sources on 64-bit RISC-V: Optimize min/max with SImode sources on 64-bit - - - - --- 2022-12-28 Raphael Moreira Zinsly New
RISC-V: Optimize permutation codegen with vcompress RISC-V: Optimize permutation codegen with vcompress - - - - --- 2023-07-11 juzhe.zhong@rivai.ai New
RISC-V: Optimize reverse series index vector RISC-V: Optimize reverse series index vector - - - - --- 2023-06-02 juzhe.zhong@rivai.ai New
RISC-V: Optimize si to di zero-extend followed by left shift. RISC-V: Optimize si to di zero-extend followed by left shift. - - - - --- 2020-05-31 Jim Wilson New
RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w - - - - --- 2022-11-08 Philipp Tomsich New
RISC-V: Optimize the MASK opt generation RISC-V: Optimize the MASK opt generation - - - - --- 2023-03-01 Feng Wang New
RISC-V: Optimize the code gen of VLM/VSM. RISC-V: Optimize the code gen of VLM/VSM. - - - - --- 2023-02-11 Li, Pan2 via Gcc-patches New
RISC-V: Optimize vsetvl AVL for VLS VLMAX auto-vectorization RISC-V: Optimize vsetvl AVL for VLS VLMAX auto-vectorization - - - - --- 2023-05-13 juzhe.zhong@rivai.ai New
RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743] RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743] - - - - --- 2023-05-06 juzhe.zhong@rivai.ai New
RISC-V: Optimize zbb ins sext.b and sext.h in rv64 RISC-V: Optimize zbb ins sext.b and sext.h in rv64 - - - - --- 2023-03-24 Feng Wang New
RISC-V: Optimized for strided load/store with stride == element width[PR111450] RISC-V: Optimized for strided load/store with stride == element width[PR111450] - - - - --- 2023-09-21 Li Xu New
RISC-V: Pass --no-relax to linker if -mno-relax is present. RISC-V: Pass --no-relax to linker if -mno-relax is present. - - - - --- 2018-04-18 Kito Cheng New
RISC-V: Pass -mno-relax through to assembler if supported RISC-V: Pass -mno-relax through to assembler if supported - - - - --- 2018-11-18 Jessica Clarke New
RISC-V: Pass abi to g++ rvv testsuite RISC-V: Pass abi to g++ rvv testsuite - - - - --- 2023-10-26 Patrick O'Neill New
RISC-V: Pattern name fix mul*3_highpart -> smul*3_highpart. RISC-V: Pattern name fix mul*3_highpart -> smul*3_highpart. - - - - --- 2021-09-28 Jim Wilson New
RISC-V: Pattern name fix mulm3_highpart -> smulm3_highpart. RISC-V: Pattern name fix mulm3_highpart -> smulm3_highpart. - - - - --- 2021-09-27 Geng Qi New
RISC-V: Point our Python scripts at python3 RISC-V: Point our Python scripts at python3 - - - - --- 2024-02-09 Palmer Dabbelt New
RISC-V: Postpone full available optimization [VSETVL PASS] RISC-V: Postpone full available optimization [VSETVL PASS] - - - - --- 2023-12-13 juzhe.zhong@rivai.ai New
RISC-V: Preserve arch version info during normalizing arch string RISC-V: Preserve arch version info during normalizing arch string - - - - --- 2020-06-30 Kito Cheng New
RISC-V: Produce better code with complex constants [PR95632] [PR106602] RISC-V: Produce better code with complex constants [PR95632] [PR106602] - - - - --- 2022-12-07 Raphael Moreira Zinsly New
RISC-V: Prohibit combination of 'E' and 'H' RISC-V: Prohibit combination of 'E' and 'H' - - - - --- 2023-10-21 Tsukasa OI New
RISC-V: Promode modes of constant loads for store insns. RISC-V: Promode modes of constant loads for store insns. - - - - --- 2019-04-27 Jim Wilson New
RISC-V: Promote type correctly for libcalls RISC-V: Promote type correctly for libcalls - - - - --- 2019-08-01 Kito Cheng New
RISC-V: Properly parse the letter 'p' in '-march'. RISC-V: Properly parse the letter 'p' in '-march'. - - - - --- 2021-05-18 Geng Qi New
RISC-V: Properly parse the letter 'p' in '-march'. RISC-V: Properly parse the letter 'p' in '-march'. - - - - --- 2021-05-17 Geng Qi New
RISC-V: RVV: add toggle to control vsetvl pass behavior RISC-V: RVV: add toggle to control vsetvl pass behavior - - - - --- 2023-12-22 Vineet Gupta New
RISC-V: Raise error on unexpected ISA string at end. RISC-V: Raise error on unexpected ISA string at end. - - - - --- 2019-07-31 Maxim Blinov New
RISC-V: Re-enable -msave-restore for shared libraries. RISC-V: Re-enable -msave-restore for shared libraries. - - - - --- 2019-09-07 Jim Wilson New
RISC-V: Rearrange the organization of declarations of RVV intrinsics [NFC] RISC-V: Rearrange the organization of declarations of RVV intrinsics [NFC] - - - - --- 2023-02-14 juzhe.zhong@rivai.ai New
RISC-V: Recognize stepped series in expand_vec_perm_const. RISC-V: Recognize stepped series in expand_vec_perm_const. - - - - --- 2023-12-09 Robin Dapp New
RISC-V: Recognized Svinval and Svnapot extensions RISC-V: Recognized Svinval and Svnapot extensions - - - - --- 2022-10-25 Monk Chiang New
RISC-V: Refactor Dynamic LMUL codes RISC-V: Refactor Dynamic LMUL codes - - - - --- 2023-12-12 juzhe.zhong@rivai.ai New
RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS - - - - --- 2023-08-21 juzhe.zhong@rivai.ai New
RISC-V: Refactor RVV iterators[NFC] RISC-V: Refactor RVV iterators[NFC] - - - - --- 2023-11-18 juzhe.zhong@rivai.ai New
RISC-V: Refactor RVV machine modes RISC-V: Refactor RVV machine modes - - - - --- 2023-07-19 juzhe.zhong@rivai.ai New
RISC-V: Refactor and clean emit_{vlmax, nonvlmax}_xxx functions RISC-V: Refactor and clean emit_{vlmax, nonvlmax}_xxx functions - - - - --- 2023-08-30 Lehua Ding New
RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} - - - - --- 2023-08-25 Lehua Ding New
RISC-V: Refactor and cleanup fma patterns RISC-V: Refactor and cleanup fma patterns - - - - --- 2023-09-18 Lehua Ding New
RISC-V: Refactor and cleanup vsetvl pass RISC-V: Refactor and cleanup vsetvl pass - - - - --- 2023-10-16 Lehua Ding New
RISC-V: Refactor expand_reduction and cleanup enum reduction_type RISC-V: Refactor expand_reduction and cleanup enum reduction_type - - - - --- 2023-09-15 Lehua Ding New
RISC-V: Refactor requirement of ZVFH and ZVFHMIN. RISC-V: Refactor requirement of ZVFH and ZVFHMIN. - - - - --- 2023-06-07 Li, Pan2 via Gcc-patches New
RISC-V: Refactor the framework of RVV auto-vectorization RISC-V: Refactor the framework of RVV auto-vectorization - - - - --- 2023-05-23 juzhe.zhong@rivai.ai New
RISC-V: Refactor the integer ternary autovec pattern RISC-V: Refactor the integer ternary autovec pattern - - - - --- 2023-06-21 juzhe.zhong@rivai.ai New
RISC-V: Refactor the or pattern to switch cases RISC-V: Refactor the or pattern to switch cases - - - - --- 2023-05-14 Li, Pan2 via Gcc-patches New
RISC-V: Refine Phase 3 of VSETVL PASS RISC-V: Refine Phase 3 of VSETVL PASS - - - - --- 2023-01-04 juzhe.zhong@rivai.ai New
RISC-V: Refine codes in backward fusion RISC-V: Refine codes in backward fusion - - - - --- 2023-01-09 juzhe.zhong@rivai.ai New
RISC-V: Refine function args of some functions. RISC-V: Refine function args of some functions. - - - - --- 2023-01-18 juzhe.zhong@rivai.ai New
RISC-V: Refine reduction RA constraint according to RVV ISA RISC-V: Refine reduction RA constraint according to RVV ISA - - - - --- 2023-03-13 juzhe.zhong@rivai.ai New
RISC-V: Refine register_builtin_types function. RISC-V: Refine register_builtin_types function. - - - - --- 2022-10-11 juzhe.zhong@rivai.ai New
RISC-V: Refine riscv-vector-builtins.o include files and makefile. RISC-V: Refine riscv-vector-builtins.o include files and makefile. - - - - --- 2022-10-11 juzhe.zhong@rivai.ai New
RISC-V: Refine the condition for add additional vars in RVV cost model RISC-V: Refine the condition for add additional vars in RVV cost model - - - - --- 2024-03-28 Demin Han New
RISC-V: Refine unsigned avg_floor/avg_ceil RISC-V: Refine unsigned avg_floor/avg_ceil - - - - --- 2024-01-10 juzhe.zhong@rivai.ai New
RISC-V: Remove "extern“ for namespace [NFC] RISC-V: Remove "extern“ for namespace [NFC] - - - - --- 2023-02-14 juzhe.zhong@rivai.ai New
RISC-V: Remove @ of vec_series RISC-V: Remove @ of vec_series - - - - --- 2023-10-04 juzhe.zhong@rivai.ai New
RISC-V: Remove DCE in VSETVL PASS RISC-V: Remove DCE in VSETVL PASS - - - - --- 2023-01-18 juzhe.zhong@rivai.ai New
RISC-V: Remove FRM for vfncvt.rod instruction RISC-V: Remove FRM for vfncvt.rod instruction - - - - --- 2023-05-31 juzhe.zhong@rivai.ai New
RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion) RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion) - - - - --- 2023-05-31 juzhe.zhong@rivai.ai New
RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening conversion) RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening conversion) - - - - --- 2023-05-31 juzhe.zhong@rivai.ai New
RISC-V: Remove FRM_REGNUM dependency for rtx conversions RISC-V: Remove FRM_REGNUM dependency for rtx conversions - - - - --- 2023-05-24 juzhe.zhong@rivai.ai New
RISC-V: Remove TUPLE size macro define. RISC-V: Remove TUPLE size macro define. - - - - --- 2022-10-11 juzhe.zhong@rivai.ai New
RISC-V: Remove XFAIL of ssa-dom-cse-2.c RISC-V: Remove XFAIL of ssa-dom-cse-2.c - - - - --- 2023-10-11 juzhe.zhong@rivai.ai New
RISC-V: Remove autovec-vls.md file and clean up VLS move modes[NFC] RISC-V: Remove autovec-vls.md file and clean up VLS move modes[NFC] - - - - --- 2023-09-18 juzhe.zhong@rivai.ai New
RISC-V: Remove dirty_pat since it is redundant RISC-V: Remove dirty_pat since it is redundant - - - - --- 2023-01-09 juzhe.zhong@rivai.ai New
RISC-V: Remove duplicate `#include "riscv-vector-switch.def"` RISC-V: Remove duplicate `#include "riscv-vector-switch.def"` - - - - --- 2023-06-13 Lehua Ding New
RISC-V: Remove duplicate `order_operator' predicate RISC-V: Remove duplicate `order_operator' predicate - - - - --- 2023-11-19 Maciej W. Rozycki New
RISC-V: Remove duplicate backslashes from `stack_protect_set_<mode>' RISC-V: Remove duplicate backslashes from `stack_protect_set_<mode>' - - - - --- 2022-07-26 Maciej W. Rozycki New
RISC-V: Remove earlyclobber for wx/wf instructions. RISC-V: Remove earlyclobber for wx/wf instructions. - - - - --- 2023-11-30 juzhe.zhong@rivai.ai New
RISC-V: Remove earlyclobber from widen reduction RISC-V: Remove earlyclobber from widen reduction - - - - --- 2023-12-04 juzhe.zhong@rivai.ai New
RISC-V: Remove incorrect earliest vsetvl post optimization[PR111313] RISC-V: Remove incorrect earliest vsetvl post optimization[PR111313] - - - - --- 2023-09-07 juzhe.zhong@rivai.ai New
RISC-V: Remove incorrect function gate gather_scatter_valid_offset_mode_p RISC-V: Remove incorrect function gate gather_scatter_valid_offset_mode_p - - - - --- 2023-11-25 juzhe.zhong@rivai.ai New
RISC-V: Remove masking third operand of rotate instructions RISC-V: Remove masking third operand of rotate instructions - - - - --- 2023-05-10 Jivan Hakobyan New
RISC-V: Remove math.h import to resolve missing stubs failures RISC-V: Remove math.h import to resolve missing stubs failures - - - 2 --- 2023-09-20 Patrick O'Neill New
RISC-V: Remove movmisalign pattern for VLA modes RISC-V: Remove movmisalign pattern for VLA modes - - - - --- 2023-08-29 juzhe.zhong@rivai.ai New
RISC-V: Remove non-existing 'Zve32d' extension RISC-V: Remove non-existing 'Zve32d' extension - - - - --- 2023-08-09 Tsukasa OI New
RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412] RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412] - - - - --- 2023-09-18 Li Xu New
RISC-V: Remove poly selftest when --preference=fixed-vlmax RISC-V: Remove poly selftest when --preference=fixed-vlmax - - - - --- 2023-12-11 juzhe.zhong@rivai.ai New
RISC-V: Remove redundant attributes RISC-V: Remove redundant attributes - - - - --- 2023-01-27 juzhe.zhong@rivai.ai New
RISC-V: Remove redundant functions RISC-V: Remove redundant functions - - - - --- 2023-09-11 juzhe.zhong@rivai.ai New
RISC-V: Remove redundant printf of abs-run.c RISC-V: Remove redundant printf of abs-run.c - - - - --- 2023-05-29 juzhe.zhong@rivai.ai New
RISC-V: Remove redundant vcond patterns RISC-V: Remove redundant vcond patterns - - - - --- 2023-06-26 juzhe.zhong@rivai.ai New
RISC-V: Remove redundant vec_duplicate pattern RISC-V: Remove redundant vec_duplicate pattern - - - - --- 2023-09-18 juzhe.zhong@rivai.ai New
RISC-V: Remove redundant vlmul_ext_* patterns to fix PR110109 RISC-V: Remove redundant vlmul_ext_* patterns to fix PR110109 - - - - --- 2023-06-04 juzhe.zhong@rivai.ai New
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