diff mbox

[v4,1/5] target: add symbols for i386/x86_64 cpu features

Message ID 1341528156-4197-2-git-send-email-s.martin49@gmail.com
State Accepted
Headers show

Commit Message

Samuel Martin July 5, 2012, 10:42 p.m. UTC 
Selecting the target architecture variant automatically selects the
appropriated set of features.

Signed-off-by: Samuel Martin <s.martin49@gmail.com>

Comments

Arnout Vandecappelle July 10, 2012, 6:11 a.m. UTC | #1 
On 07/06/12 00:42, Samuel Martin wrote:
[snip]
> +config BR2_X86_CPU_HAS_SSE41
> +	bool
> +config BR2_X86_CPU_HAS_SSE42
> +	bool
> +config BR2_X86_CPU_HAS_SSE4
> +	bool
> +config BR2_X86_CPU_HAS_SSE4A
> +	bool

  I don't like these SSE4 configs which are not selected by anything.  I understand
that you need them for OpenCV, but it's not ideal.

  Maybe we need an extra subarchitecture config option to explicitly enable these?
They should depend on core2 || barcelona, probably.

  Regards,
  Arnout
Thomas Petazzoni July 13, 2012, 9:26 p.m. UTC | #2 
Le Tue, 10 Jul 2012 08:11:34 +0200,
Arnout Vandecappelle <arnout@mind.be> a écrit :

>   I don't like these SSE4 configs which are not selected by anything.  I understand
> that you need them for OpenCV, but it's not ideal.
> 
>   Maybe we need an extra subarchitecture config option to explicitly enable these?

Agreed, we should either have subarchitecture options that use those
SSE4 options, or we should not add those SSE4 options, and only add
them when those subarchitectures are added.

Samuel, can you take this into account and respin the patch set?

Thanks!

Thomas
Samuel Martin July 13, 2012, 9:57 p.m. UTC | #3 
Hi,

2012/7/13 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>:
> Le Tue, 10 Jul 2012 08:11:34 +0200,
> Arnout Vandecappelle <arnout@mind.be> a écrit :
>
>>   I don't like these SSE4 configs which are not selected by anything.  I understand
>> that you need them for OpenCV, but it's not ideal.
>>
>>   Maybe we need an extra subarchitecture config option to explicitly enable these?
>
> Agreed, we should either have subarchitecture options that use those
> SSE4 options, or we should not add those SSE4 options, and only add
> them when those subarchitectures are added.
>
> Samuel, can you take this into account and respin the patch set?
Of course.

You prefer expressing dependencies using "depends on" keyword instead
"select", is it right?

I'm not sure I got what you mean by "having subarchitecture options",
could you explain?

Cheers,
Thomas Petazzoni July 13, 2012, 10:46 p.m. UTC | #4 
Le Fri, 13 Jul 2012 23:57:15 +0200,
Samuel Martin <s.martin49@gmail.com> a écrit :

> You prefer expressing dependencies using "depends on" keyword instead
> "select", is it right?

It depends on the case. Which case are you talking about?

> I'm not sure I got what you mean by "having subarchitecture options",
> could you explain?

The different MMX, SSE, SSE2, SSE3 options are selected by the
"Architecture Variant" options. However, the SSE4 options are not
selected by any "Architecture Variant" that currently exists in
Buildroot. I'd prefer not to have such dead/unused code, so either the
corresponding Architecture Variants should be added, or the SSE4
related options should not be added for now (until someone actually
needs those Architecture Variants).

Regards,

Thomas
diff mbox

Patch

diff --git a/target/Config.in.arch b/target/Config.in.arch
index c9bbc12..590726a 100644
--- a/target/Config.in.arch
+++ b/target/Config.in.arch
@@ -325,6 +325,31 @@  endchoice
 # gcc builds libstdc++ differently depending on the
 # host tuplet given to it, so let people choose
 #
+
+# i386/x86_64 cpu features
+config BR2_X86_CPU_HAS_MMX
+	bool
+config BR2_X86_CPU_HAS_SSE
+	bool
+config BR2_X86_CPU_HAS_SSE2
+	bool
+config BR2_X86_CPU_HAS_SSE3
+	bool
+config BR2_X86_CPU_HAS_SSSE3
+	bool
+config BR2_X86_CPU_HAS_SSE41
+	bool
+config BR2_X86_CPU_HAS_SSE42
+	bool
+config BR2_X86_CPU_HAS_SSE4
+	bool
+config BR2_X86_CPU_HAS_SSE4A
+	bool
+config BR2_X86_CPU_HAS_3DNOW
+	bool
+config BR2_X86_CPU_HAS_ABM
+	bool
+
 choice
 	prompt "Target Architecture Variant"
 	depends on BR2_i386
@@ -344,46 +369,106 @@  config BR2_x86_pentiumpro
 	bool "pentium pro"
 config BR2_x86_pentium_mmx
 	bool "pentium MMX"
+	select BR2_X86_CPU_HAS_MMX
 config BR2_x86_pentium_m
 	bool "pentium mobile"
 config BR2_x86_pentium2
 	bool "pentium2"
+	select BR2_X86_CPU_HAS_MMX
 config BR2_x86_pentium3
 	bool "pentium3"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
 config BR2_x86_pentium4
 	bool "pentium4"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
 config BR2_x86_prescott
 	bool "prescott"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
 config BR2_x86_nocona
 	bool "nocona"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
 config BR2_x86_core2
 	bool "core2"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
+	select BR2_X86_CPU_HAS_SSSE3
 config BR2_x86_atom
 	bool "atom"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
+	select BR2_X86_CPU_HAS_SSSE3
 config BR2_x86_k6
 	bool "k6"
+	select BR2_X86_CPU_HAS_MMX
 config BR2_x86_k6_2
 	bool "k6-2"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
 config BR2_x86_athlon
 	bool "athlon"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
 config BR2_x86_athlon_4
 	bool "athlon-4"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
+	select BR2_X86_CPU_HAS_SSE
 config BR2_x86_opteron
 	bool "opteron"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
 config BR2_x86_opteron_sse3
 	bool "opteron w/ SSE3"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
 config BR2_x86_barcelona
 	bool "barcelona"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
+	select BR2_X86_CPU_HAS_SSE4A
+	select BR2_X86_CPU_HAS_ABM
 config BR2_x86_geode
 	bool "geode"
+	# Don't include MMX support because there several variant of geode
+	# processor, some with MMX support, some without.
+	# See: http://en.wikipedia.org/wiki/Geode_%28processor%29
+	select BR2_X86_CPU_HAS_3DNOW
 config BR2_x86_c3
 	bool "Via/Cyrix C3 (Samuel/Ezra cores)"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
 config BR2_x86_c32
 	bool "Via C3-2 (Nehemiah cores)"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
 config BR2_x86_winchip_c6
 	bool "IDT Winchip C6"
+	select BR2_X86_CPU_HAS_MMX
 config BR2_x86_winchip2
 	bool "IDT Winchip 2"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
 endchoice
 
 choice
@@ -397,16 +482,46 @@  config BR2_x86_64_generic
 	bool "generic"
 config BR2_x86_64_barcelona
 	bool "barcelona"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
+	select BR2_X86_CPU_HAS_SSE4A
+	select BR2_X86_CPU_HAS_ABM
 config BR2_x86_64_opteron_sse3
 	bool "opteron w/ sse3"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
 config BR2_x86_64_opteron
 	bool "opteron"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
 config BR2_x86_64_nocona
 	bool "nocona"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
 config BR2_x86_64_core2
 	bool "core2"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
+	select BR2_X86_CPU_HAS_SSSE3
 config BR2_x86_64_atom
 	bool "atom"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
+	select BR2_X86_CPU_HAS_SSSE3
 endchoice
 
 choice