From patchwork Thu Jul 5 22:42:32 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Martin X-Patchwork-Id: 169289 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from whitealder.osuosl.org (whitealder.osuosl.org [140.211.166.138]) by ozlabs.org (Postfix) with ESMTP id 9E3B52C01D3 for ; Fri, 6 Jul 2012 08:45:14 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 788AA8964D; Thu, 5 Jul 2012 22:45:10 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3JWoveCzKEYq; Thu, 5 Jul 2012 22:44:59 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by whitealder.osuosl.org (Postfix) with ESMTP id 12E918CA8D; Thu, 5 Jul 2012 22:44:53 +0000 (UTC) X-Original-To: buildroot@lists.busybox.net Delivered-To: buildroot@osuosl.org Received: from whitealder.osuosl.org (whitealder.osuosl.org [140.211.166.138]) by ash.osuosl.org (Postfix) with ESMTP id 137398F753 for ; Thu, 5 Jul 2012 22:44:25 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id F2F0489DBA for ; Thu, 5 Jul 2012 22:44:24 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VkrcXwWLwn7O for ; Thu, 5 Jul 2012 22:44:19 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mail-wi0-f181.google.com (mail-wi0-f181.google.com [209.85.212.181]) by whitealder.osuosl.org (Postfix) with ESMTPS id 5A2CE86572 for ; Thu, 5 Jul 2012 22:44:19 +0000 (UTC) Received: by wibhm2 with SMTP id hm2so130794wib.10 for ; Thu, 05 Jul 2012 15:44:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=zfoXNFCFoSQComA5R4PgSt4lZmkkpg1JxATfAphOP30=; b=XRRMx/lRHWG2DUXI1iUI7HJfk8jNu8Ak9CRxZ/3e74nXNUO/ZvX4wcwdoH2ujf5IXY aBZbWmFzTM/ZpKpEE/LlNuwSXEnH8S5fKX2XQ8UJLhmwVSPv1oSR5QRETemvre4HXpzo lDpsgsTQGJWTDmn8j2fWGcr61dpPRLzzQNhjULTAUR2EuCefc4aUsxTIMb2j5nmJX3Ns kTti0jfpM+nwuawfqYry5MlkPmJkQ3/55e/Xv/Lmfp1lgvEikTPJunjO1D9dot6OZwkg RIFPNiUJEYePeq4J5u3bApmBfR1Pkr5BurCoA1ynsR0OlmSGQeu8gFNx6bmiuAGUl9Jw hnfA== Received: by 10.180.98.138 with SMTP id ei10mr2921339wib.1.1341528255176; Thu, 05 Jul 2012 15:44:15 -0700 (PDT) Received: from localhost.localdomain (ivr94-4-82-229-165-48.fbx.proxad.net. [82.229.165.48]) by mx.google.com with ESMTPS id j6sm3868134wiy.4.2012.07.05.15.44.13 (version=SSLv3 cipher=OTHER); Thu, 05 Jul 2012 15:44:14 -0700 (PDT) From: Samuel Martin To: buildroot@busybox.net Date: Fri, 6 Jul 2012 00:42:32 +0200 Message-Id: <1341528156-4197-2-git-send-email-s.martin49@gmail.com> X-Mailer: git-send-email 1.7.11.1 In-Reply-To: <1341528156-4197-1-git-send-email-s.martin49@gmail.com> References: <1341528156-4197-1-git-send-email-s.martin49@gmail.com> Subject: [Buildroot] [PATCH v4 1/5] target: add symbols for i386/x86_64 cpu features X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.14 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: buildroot-bounces@busybox.net Sender: buildroot-bounces@busybox.net Selecting the target architecture variant automatically selects the appropriated set of features. Signed-off-by: Samuel Martin diff --git a/target/Config.in.arch b/target/Config.in.arch index c9bbc12..590726a 100644 --- a/target/Config.in.arch +++ b/target/Config.in.arch @@ -325,6 +325,31 @@ endchoice # gcc builds libstdc++ differently depending on the # host tuplet given to it, so let people choose # + +# i386/x86_64 cpu features +config BR2_X86_CPU_HAS_MMX + bool +config BR2_X86_CPU_HAS_SSE + bool +config BR2_X86_CPU_HAS_SSE2 + bool +config BR2_X86_CPU_HAS_SSE3 + bool +config BR2_X86_CPU_HAS_SSSE3 + bool +config BR2_X86_CPU_HAS_SSE41 + bool +config BR2_X86_CPU_HAS_SSE42 + bool +config BR2_X86_CPU_HAS_SSE4 + bool +config BR2_X86_CPU_HAS_SSE4A + bool +config BR2_X86_CPU_HAS_3DNOW + bool +config BR2_X86_CPU_HAS_ABM + bool + choice prompt "Target Architecture Variant" depends on BR2_i386 @@ -344,46 +369,106 @@ config BR2_x86_pentiumpro bool "pentium pro" config BR2_x86_pentium_mmx bool "pentium MMX" + select BR2_X86_CPU_HAS_MMX config BR2_x86_pentium_m bool "pentium mobile" config BR2_x86_pentium2 bool "pentium2" + select BR2_X86_CPU_HAS_MMX config BR2_x86_pentium3 bool "pentium3" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE config BR2_x86_pentium4 bool "pentium4" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 config BR2_x86_prescott bool "prescott" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 config BR2_x86_nocona bool "nocona" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 config BR2_x86_core2 bool "core2" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 config BR2_x86_atom bool "atom" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 config BR2_x86_k6 bool "k6" + select BR2_X86_CPU_HAS_MMX config BR2_x86_k6_2 bool "k6-2" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_3DNOW config BR2_x86_athlon bool "athlon" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_3DNOW config BR2_x86_athlon_4 bool "athlon-4" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_3DNOW + select BR2_X86_CPU_HAS_SSE config BR2_x86_opteron bool "opteron" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_3DNOW + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 config BR2_x86_opteron_sse3 bool "opteron w/ SSE3" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_3DNOW + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 config BR2_x86_barcelona bool "barcelona" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_3DNOW + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSE4A + select BR2_X86_CPU_HAS_ABM config BR2_x86_geode bool "geode" + # Don't include MMX support because there several variant of geode + # processor, some with MMX support, some without. + # See: http://en.wikipedia.org/wiki/Geode_%28processor%29 + select BR2_X86_CPU_HAS_3DNOW config BR2_x86_c3 bool "Via/Cyrix C3 (Samuel/Ezra cores)" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_3DNOW config BR2_x86_c32 bool "Via C3-2 (Nehemiah cores)" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE config BR2_x86_winchip_c6 bool "IDT Winchip C6" + select BR2_X86_CPU_HAS_MMX config BR2_x86_winchip2 bool "IDT Winchip 2" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_3DNOW endchoice choice @@ -397,16 +482,46 @@ config BR2_x86_64_generic bool "generic" config BR2_x86_64_barcelona bool "barcelona" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_3DNOW + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSE4A + select BR2_X86_CPU_HAS_ABM config BR2_x86_64_opteron_sse3 bool "opteron w/ sse3" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_3DNOW + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 config BR2_x86_64_opteron bool "opteron" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_3DNOW + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 config BR2_x86_64_nocona bool "nocona" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 config BR2_x86_64_core2 bool "core2" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 config BR2_x86_64_atom bool "atom" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 endchoice choice