| Message ID | 768f00ff8dfbbf4e7e481ad7225cb1723d2799bb.1674182603.git.Takahiro.Kuwano@infineon.com |
|---|---|
| State | Accepted |
| Commit | ee7296bbcd6bae3ded087cb56c786da10aa6fc6a |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
| Series | Keep CFR5V[6] as 1 in Octal DTR enable | expand |
On 1/20/23 03:28, tkuw584924@gmail.com wrote: > From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> > > CFR5[6] is reserved bit and must be always 1. Set it to comply with flash > requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN definition, > stop using magic numbers and describe the missing bit fields in CFR5 > register. This is useful for both readability and future possible addition > of Octal STR mode support. > > Fixes: ea9a22f7e79c ("mtd: spi-nor-core: Add support for Cypress Semper flash") > Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> > Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> > --- > include/linux/mtd/spi-nor.h | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index 30f15452aa68..2fb4595fc756 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -194,7 +194,12 @@ > #define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */ > #define SPINOR_REG_CYPRESS_CFR3V_UNISECT BIT(3) /* Uniform sector mode */ > #define SPINOR_REG_CYPRESS_CFR5V 0x00800006 > -#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN 0x3 > +#define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) > +#define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1) > +#define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0) > +#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN \ > + (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \ > + SPINOR_REG_CYPRESS_CFR5_OPI) > #define SPINOR_OP_CYPRESS_RD_FAST 0xee > > /* Supported SPI protocols */
On 20/01/23 08:58, tkuw584924@gmail.com wrote: > From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> > > CFR5[6] is reserved bit and must be always 1. Set it to comply with flash > requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN definition, > stop using magic numbers and describe the missing bit fields in CFR5 > register. This is useful for both readability and future possible addition > of Octal STR mode support. > > Fixes: ea9a22f7e79c ("mtd: spi-nor-core: Add support for Cypress Semper flash") > Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> > Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> > --- Reviewed-by: Dhruva Gole <d-gole@ti.com> > include/linux/mtd/spi-nor.h | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index 30f15452aa68..2fb4595fc756 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -194,7 +194,12 @@ > #define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */ > #define SPINOR_REG_CYPRESS_CFR3V_UNISECT BIT(3) /* Uniform sector mode */ > #define SPINOR_REG_CYPRESS_CFR5V 0x00800006 > -#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN 0x3 > +#define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) > +#define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1) > +#define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0) > +#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN \ > + (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \ > + SPINOR_REG_CYPRESS_CFR5_OPI) > #define SPINOR_OP_CYPRESS_RD_FAST 0xee > > /* Supported SPI protocols */
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 30f15452aa68..2fb4595fc756 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -194,7 +194,12 @@ #define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */ #define SPINOR_REG_CYPRESS_CFR3V_UNISECT BIT(3) /* Uniform sector mode */ #define SPINOR_REG_CYPRESS_CFR5V 0x00800006 -#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN 0x3 +#define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) +#define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1) +#define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0) +#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN \ + (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \ + SPINOR_REG_CYPRESS_CFR5_OPI) #define SPINOR_OP_CYPRESS_RD_FAST 0xee /* Supported SPI protocols */