diff mbox series

[v2,2/2] mtd: spi-nor-core: Make CFRx reg fields generic

Message ID 0d682dac20c031767aa9187357ed477b905c86fc.1674182603.git.Takahiro.Kuwano@infineon.com
State Accepted
Commit da16d72efd004e046b8b4f98a662afd4bef09206
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series Keep CFR5V[6] as 1 in Octal DTR enable | expand

Commit Message

Takahiro Kuwano Jan. 20, 2023, 3:28 a.m. UTC 
From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>

Cypress defines two flavors of configuration registers, volatile and
non volatile, and both use the same bit fields. Rename the bitfields in
the configuration registers so that they can be used for both flavors.

Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
---
 drivers/mtd/spi/spi-nor-core.c | 8 ++++----
 include/linux/mtd/spi-nor.h    | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

Comments

Tudor Ambarus Jan. 20, 2023, 7:19 a.m. UTC | #1 
On 1/20/23 03:28, tkuw584924@gmail.com wrote:
> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> 
> Cypress defines two flavors of configuration registers, volatile and
> non volatile, and both use the same bit fields. Rename the bitfields in
> the configuration registers so that they can be used for both flavors.
> 
> Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org>
> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>

Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>

> ---
>   drivers/mtd/spi/spi-nor-core.c | 8 ++++----
>   include/linux/mtd/spi-nor.h    | 8 ++++----
>   2 files changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index 1ea8363d9f89..a3198253ca63 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -3373,7 +3373,7 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor)
>   	if (ret)
>   		return ret;
>   
> -	buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;
> +	buf = SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24;
>   	op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
>   			SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR2V, 1),
>   			SPI_MEM_OP_NO_DUMMY,
> @@ -3396,7 +3396,7 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor)
>   	if (ret)
>   		return ret;
>   
> -	buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
> +	buf = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN;
>   	op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
>   			SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR5V, 1),
>   			SPI_MEM_OP_NO_DUMMY,
> @@ -3444,7 +3444,7 @@ static int s28hx_t_setup(struct spi_nor *nor, const struct flash_info *info,
>   	if (ret)
>   		return ret;
>   
> -	if (!(buf & SPINOR_REG_CYPRESS_CFR3V_UNISECT))
> +	if (!(buf & SPINOR_REG_CYPRESS_CFR3_UNISECT))
>   		nor->erase = s28hx_t_erase_non_uniform;
>   
>   	return spi_nor_default_setup(nor, info, params);
> @@ -3511,7 +3511,7 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor,
>   	if (ret)
>   		return ret;
>   
> -	if (buf & SPINOR_REG_CYPRESS_CFR3V_PGSZ)
> +	if (buf & SPINOR_REG_CYPRESS_CFR3_PGSZ)
>   		params->page_size = 512;
>   	else
>   		params->page_size = 256;
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index 2fb4595fc756..605cddef4d06 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -189,15 +189,15 @@
>   #define SPINOR_OP_WR_ANY_REG			0x71	/* Write any register */
>   #define SPINOR_OP_S28_SE_4K			0x21
>   #define SPINOR_REG_CYPRESS_CFR2V		0x00800003
> -#define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24	0xb
> +#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24	0xb
>   #define SPINOR_REG_CYPRESS_CFR3V		0x00800004
> -#define SPINOR_REG_CYPRESS_CFR3V_PGSZ		BIT(4) /* Page size. */
> -#define SPINOR_REG_CYPRESS_CFR3V_UNISECT	BIT(3) /* Uniform sector mode */
> +#define SPINOR_REG_CYPRESS_CFR3_PGSZ		BIT(4) /* Page size. */
> +#define SPINOR_REG_CYPRESS_CFR3_UNISECT		BIT(3) /* Uniform sector mode */
>   #define SPINOR_REG_CYPRESS_CFR5V		0x00800006
>   #define SPINOR_REG_CYPRESS_CFR5_BIT6		BIT(6)
>   #define SPINOR_REG_CYPRESS_CFR5_DDR		BIT(1)
>   #define SPINOR_REG_CYPRESS_CFR5_OPI		BIT(0)
> -#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN				\
> +#define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN				\
>   	(SPINOR_REG_CYPRESS_CFR5_BIT6 |	SPINOR_REG_CYPRESS_CFR5_DDR |	\
>   	 SPINOR_REG_CYPRESS_CFR5_OPI)
>   #define SPINOR_OP_CYPRESS_RD_FAST		0xee
Dhruva Gole Jan. 23, 2023, 7:43 a.m. UTC | #2 
On 20/01/23 08:58, tkuw584924@gmail.com wrote:
> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>
> Cypress defines two flavors of configuration registers, volatile and
> non volatile, and both use the same bit fields. Rename the bitfields in
> the configuration registers so that they can be used for both flavors.
>
> Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org>
> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> ---

Reviewed-by: Dhruva Gole <d-gole@ti.com>

>   drivers/mtd/spi/spi-nor-core.c | 8 ++++----
>   include/linux/mtd/spi-nor.h    | 8 ++++----
>   2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index 1ea8363d9f89..a3198253ca63 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -3373,7 +3373,7 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor)
>   	if (ret)
>   		return ret;
>   
> -	buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;
> +	buf = SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24;
>   	op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
>   			SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR2V, 1),
>   			SPI_MEM_OP_NO_DUMMY,
> @@ -3396,7 +3396,7 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor)
>   	if (ret)
>   		return ret;
>   
> -	buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
> +	buf = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN;
>   	op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
>   			SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR5V, 1),
>   			SPI_MEM_OP_NO_DUMMY,
> @@ -3444,7 +3444,7 @@ static int s28hx_t_setup(struct spi_nor *nor, const struct flash_info *info,
>   	if (ret)
>   		return ret;
>   
> -	if (!(buf & SPINOR_REG_CYPRESS_CFR3V_UNISECT))
> +	if (!(buf & SPINOR_REG_CYPRESS_CFR3_UNISECT))
>   		nor->erase = s28hx_t_erase_non_uniform;
>   
>   	return spi_nor_default_setup(nor, info, params);
> @@ -3511,7 +3511,7 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor,
>   	if (ret)
>   		return ret;
>   
> -	if (buf & SPINOR_REG_CYPRESS_CFR3V_PGSZ)
> +	if (buf & SPINOR_REG_CYPRESS_CFR3_PGSZ)
>   		params->page_size = 512;
>   	else
>   		params->page_size = 256;
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index 2fb4595fc756..605cddef4d06 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -189,15 +189,15 @@
>   #define SPINOR_OP_WR_ANY_REG			0x71	/* Write any register */
>   #define SPINOR_OP_S28_SE_4K			0x21
>   #define SPINOR_REG_CYPRESS_CFR2V		0x00800003
> -#define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24	0xb
> +#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24	0xb
>   #define SPINOR_REG_CYPRESS_CFR3V		0x00800004
> -#define SPINOR_REG_CYPRESS_CFR3V_PGSZ		BIT(4) /* Page size. */
> -#define SPINOR_REG_CYPRESS_CFR3V_UNISECT	BIT(3) /* Uniform sector mode */
> +#define SPINOR_REG_CYPRESS_CFR3_PGSZ		BIT(4) /* Page size. */
> +#define SPINOR_REG_CYPRESS_CFR3_UNISECT		BIT(3) /* Uniform sector mode */
>   #define SPINOR_REG_CYPRESS_CFR5V		0x00800006
>   #define SPINOR_REG_CYPRESS_CFR5_BIT6		BIT(6)
>   #define SPINOR_REG_CYPRESS_CFR5_DDR		BIT(1)
>   #define SPINOR_REG_CYPRESS_CFR5_OPI		BIT(0)
> -#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN				\
> +#define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN				\
>   	(SPINOR_REG_CYPRESS_CFR5_BIT6 |	SPINOR_REG_CYPRESS_CFR5_DDR |	\
>   	 SPINOR_REG_CYPRESS_CFR5_OPI)
>   #define SPINOR_OP_CYPRESS_RD_FAST		0xee
diff mbox series

Patch

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 1ea8363d9f89..a3198253ca63 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3373,7 +3373,7 @@  static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor)
 	if (ret)
 		return ret;
 
-	buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;
+	buf = SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24;
 	op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
 			SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR2V, 1),
 			SPI_MEM_OP_NO_DUMMY,
@@ -3396,7 +3396,7 @@  static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor)
 	if (ret)
 		return ret;
 
-	buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
+	buf = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN;
 	op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
 			SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR5V, 1),
 			SPI_MEM_OP_NO_DUMMY,
@@ -3444,7 +3444,7 @@  static int s28hx_t_setup(struct spi_nor *nor, const struct flash_info *info,
 	if (ret)
 		return ret;
 
-	if (!(buf & SPINOR_REG_CYPRESS_CFR3V_UNISECT))
+	if (!(buf & SPINOR_REG_CYPRESS_CFR3_UNISECT))
 		nor->erase = s28hx_t_erase_non_uniform;
 
 	return spi_nor_default_setup(nor, info, params);
@@ -3511,7 +3511,7 @@  static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor,
 	if (ret)
 		return ret;
 
-	if (buf & SPINOR_REG_CYPRESS_CFR3V_PGSZ)
+	if (buf & SPINOR_REG_CYPRESS_CFR3_PGSZ)
 		params->page_size = 512;
 	else
 		params->page_size = 256;
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 2fb4595fc756..605cddef4d06 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -189,15 +189,15 @@ 
 #define SPINOR_OP_WR_ANY_REG			0x71	/* Write any register */
 #define SPINOR_OP_S28_SE_4K			0x21
 #define SPINOR_REG_CYPRESS_CFR2V		0x00800003
-#define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24	0xb
+#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24	0xb
 #define SPINOR_REG_CYPRESS_CFR3V		0x00800004
-#define SPINOR_REG_CYPRESS_CFR3V_PGSZ		BIT(4) /* Page size. */
-#define SPINOR_REG_CYPRESS_CFR3V_UNISECT	BIT(3) /* Uniform sector mode */
+#define SPINOR_REG_CYPRESS_CFR3_PGSZ		BIT(4) /* Page size. */
+#define SPINOR_REG_CYPRESS_CFR3_UNISECT		BIT(3) /* Uniform sector mode */
 #define SPINOR_REG_CYPRESS_CFR5V		0x00800006
 #define SPINOR_REG_CYPRESS_CFR5_BIT6		BIT(6)
 #define SPINOR_REG_CYPRESS_CFR5_DDR		BIT(1)
 #define SPINOR_REG_CYPRESS_CFR5_OPI		BIT(0)
-#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN				\
+#define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN				\
 	(SPINOR_REG_CYPRESS_CFR5_BIT6 |	SPINOR_REG_CYPRESS_CFR5_DDR |	\
 	 SPINOR_REG_CYPRESS_CFR5_OPI)
 #define SPINOR_OP_CYPRESS_RD_FAST		0xee