diff mbox series

[04/27] imx: imx8ulp: clock: Add clock support for i3c controller

Message ID 20220214124735.25580-5-peng.fan@oss.nxp.com
State Superseded
Delegated to: Stefano Babic
Headers show
Series imx: imx8ulp: misc update from downstream | expand

Commit Message

Peng Fan (OSS) Feb. 14, 2022, 12:47 p.m. UTC 
From: Clark Wang <xiaoning.wang@nxp.com>

Add i3c controller clock enable/disable function for imx8ulp.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/clock.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

Comments

Fabio Estevam Feb. 26, 2022, 1:36 p.m. UTC | #1 
On Mon, Feb 14, 2022 at 9:08 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> From: Clark Wang <xiaoning.wang@nxp.com>
>
> Add i3c controller clock enable/disable function for imx8ulp.
>
> Reviewed-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm/mach-imx/imx8ulp/clock.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
> index 91580b2c29..6f52ccee34 100644
> --- a/arch/arm/mach-imx/imx8ulp/clock.c
> +++ b/arch/arm/mach-imx/imx8ulp/clock.c
> @@ -237,6 +237,32 @@ u32 imx_get_i2cclk(u32 i2c_num)
>  }
>  #endif
>
> +#if IS_ENABLED(CONFIG_SYS_I2C_IMX_I3C)
> +int enable_i3c_clk(unsigned char enable, u32 i3c_num)
> +{
> +       if (i3c_num != 8)

What does this magic 8 mean? Please replace with some more meaningful define.

> +u32 imx_get_i3cclk(u32 i3c_num)
> +{
> +       if (i3c_num != 8)

Same here.
diff mbox series

Patch

diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index 91580b2c29..6f52ccee34 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -237,6 +237,32 @@  u32 imx_get_i2cclk(u32 i2c_num)
 }
 #endif
 
+#if IS_ENABLED(CONFIG_SYS_I2C_IMX_I3C)
+int enable_i3c_clk(unsigned char enable, u32 i3c_num)
+{
+	if (i3c_num != 8)
+		return -EINVAL;
+
+	if (enable) {
+		pcc_clock_enable(3, I3C2_PCC3_SLOT, false);
+		pcc_clock_sel(3, I3C2_PCC3_SLOT, SOSC_DIV2);
+		pcc_clock_enable(3, I3C2_PCC3_SLOT, true);
+		pcc_reset_peripheral(3, I3C2_PCC3_SLOT, false);
+	} else {
+		pcc_clock_enable(3, I3C2_PCC3_SLOT, false);
+	}
+	return 0;
+}
+
+u32 imx_get_i3cclk(u32 i3c_num)
+{
+	if (i3c_num != 8)
+		return 0;
+
+	return pcc_clock_get_rate(3, I3C2_PCC3_SLOT);
+}
+#endif
+
 void enable_usboh3_clk(unsigned char enable)
 {
 	if (enable) {