diff mbox series

[10/23] imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers

Message ID 1675154554-88217-11-git-send-email-ye.li@nxp.com
State Accepted
Commit 4e08a510d23e2e23c8a776ccea582d0acd75fd4d
Delegated to: Stefano Babic
Headers show
Series Add i.MX8ULP A1 revision support | expand

Commit Message

Ye Li Jan. 31, 2023, 8:42 a.m. UTC 
At present, in cgc1_pll3_init we don't set the pll3pfd div values,
just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2
to 1 and pfd2div1 to 3.
This finally causes some clocks' rate decreased, for example USDHC.
So clear the PLL3DIV_PFD dividers to get correct rate.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/cgc.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Stefano Babic March 29, 2023, 8:16 p.m. UTC | #1 
> At present, in cgc1_pll3_init we don't set the pll3pfd div values,
> just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2
> to 1 and pfd2div1 to 3.
> This finally causes some clocks' rate decreased, for example USDHC.
> So clear the PLL3DIV_PFD dividers to get correct rate.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic
diff mbox series

Patch

diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c
index d240aba..104109e 100644
--- a/arch/arm/mach-imx/imx8ulp/cgc.c
+++ b/arch/arm/mach-imx/imx8ulp/cgc.c
@@ -169,6 +169,9 @@  void cgc1_pll3_init(ulong freq)
 	while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(30)))
 		;
 
+	clrbits_le32(&cgc1_regs->pll3div_pfd0, 0x3f3f3f3f);
+	clrbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f);
+
 	clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7));
 	clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(15));
 	clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(23));