diff mbox series

[22/23] imx8ulp_evk: disable overflow of port0 for LPAV

Message ID 1675154554-88217-23-git-send-email-ye.li@nxp.com
State Accepted
Commit 9b7e39b6c1ff40a8336328708727394ae8a107e5
Delegated to: Stefano Babic
Headers show
Series Add i.MX8ULP A1 revision support | expand

Commit Message

Ye Li Jan. 31, 2023, 8:42 a.m. UTC
From: Peng Fan <peng.fan@nxp.com>

Bit0: Port 0 behavior when bandwidth maximized. Set to 1 to allow overflow

With overflow set, we see some issue that A35 may not able to get enough
bandwidth and A35 will report hrtimer takes too much time, workqueue
lockup. With overflow cleared, the issues are gone.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8ulp_evk/lpddr4_timing.c     | 2 +-
 board/freescale/imx8ulp_evk/lpddr4_timing_266.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

Comments

Stefano Babic March 29, 2023, 8:16 p.m. UTC | #1
> From: Peng Fan <peng.fan@nxp.com>
> Bit0: Port 0 behavior when bandwidth maximized. Set to 1 to allow overflow
> With overflow set, we see some issue that A35 may not able to get enough
> bandwidth and A35 will report hrtimer takes too much time, workqueue
> lockup. With overflow cleared, the issues are gone.
> Reviewed-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic
diff mbox series

Patch

diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk/lpddr4_timing.c
index e9edb87..6d28053 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c
@@ -396,7 +396,7 @@  struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e0608e0, 0x30f0f },	/* 568 */
 	{ 0x2e0608e4, 0xffffffff },	/* 569 */
 	{ 0x2e0608e8, 0x32070f0f },	/* 570 */
-	{ 0x2e0608ec, 0x1320001 },	/* 571 */
+	{ 0x2e0608ec, 0x1320000 },	/* 571 */
 	{ 0x2e0608f0, 0x13200 },	/* 572 */
 	{ 0x2e0608f4, 0x132 },	/* 573 */
 	{ 0x2e0608fc, 0x1b1b0000 },	/* 575 */
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
index 9728a25..7945760 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
@@ -395,7 +395,7 @@  struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e0608e0, 0x30f0f },	/* 568 */
 	{ 0x2e0608e4, 0xffffffff },	/* 569 */
 	{ 0x2e0608e8, 0x32070f0f },	/* 570 */
-	{ 0x2e0608ec, 0x1320001 },	/* 571 */
+	{ 0x2e0608ec, 0x1320000 },	/* 571 */
 	{ 0x2e0608f0, 0x13200 },	/* 572 */
 	{ 0x2e0608f4, 0x132 },	/* 573 */
 	{ 0x2e0608fc, 0x1d1b0000 },	/* 575 */