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[56/61] phb5: Fix PHB max link speed definition on P10

Message ID 20210719132012.150948-57-hegdevasant@linux.vnet.ibm.com
State Superseded
Headers show
Series P10 Enablement | expand

Commit Message

Vasant Hegde July 19, 2021, 1:20 p.m. UTC 
From: Frederic Barrat <fbarrat@linux.ibm.com>

Not all PHBs are capable of GEN5 speed on P10. In all PEC
configurations, the first PHB is the only one which can handle GEN5.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
---
 hw/phb4.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/hw/phb4.c b/hw/phb4.c
index 3c316f41e..7eb38ea46 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -3011,10 +3011,10 @@  static unsigned int phb4_get_max_link_speed(struct phb4 *p, struct dt_node *np)
 	chip = get_chip(p->chip_id);
 
 	hw_max_link_speed = 4;
-	if (is_phb5())
+	if (is_phb5() && (p->index == 0 || p->index == 3))
 		hw_max_link_speed = 5;
 
-	/* Priority order: NVRAM -> dt -> GEN3 dd2.00 -> GEN4 */
+	/* Priority order: NVRAM -> dt -> GEN3 dd2.00 -> hw default */
 	max_link_speed = hw_max_link_speed;
 	if (p->rev == PHB4_REV_NIMBUS_DD20 &&
 	    ((0xf & chip->ec_level) == 0) && chip->ec_rev == 0)